Matador DSP Family

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Matador DSP Family

• DSP and IO for Demanding Applications

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Matador Features

• All cards in series have common features
• Texas Instruments TMS320C6711/13 DSP
• 32MB SDRAM (code/data)
• 32/64 bit 33 MHz, 3V/5V PCI
• Precision time bases - DDS/timers
• Digital IO
• Field-reconfigurable, high density logic
• High-performance, dedicated IO
• Advanced trigger mechanisms
• Multi-card support
• DSP BIOS support

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Matador DSP/PCI core
Interface/control logic
JTAG
Multi-card support ClockLink/SyncLink
6711 DSP 150 MHz or 6713 DSP 225 MHz
DDS timebase
300 MB/sec
Triggering
Card Specific IO
FIFOs
Digital error correction
32 Mbytes SDRAM
PCI Interface 132/264 MB/sec burst rate 32/64
bit 5V/3V 33 MHz
FIFOPort
FIFOs
Digital IO
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Matador DSP Products
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TI DSP Evolution
Virtex II FPGA
MIPS
10000
C6414
Velocia Quixote/Quadia
Multiprocessor C6201/6701
C6400
Q6x
Quixote
Virtex FPGA
C6713
C6201/6701
225 MHz
M6x/cM6x/SBC6x
C6711
1000
150MHz
SBC6711 / Matador
Multiprocessor C44
Multiprocessor C44
100
PC44
PCI44
C549
SBC54
C31
C44
C32
M44/cM44
PC31/SBC31
PC32/SBC32
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93
94
95
96
97
98
99
00
01
02
03
04
Year
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Differences 6711 and 6713
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Advantages of Matador Cards

• Integrated analog IO
• Improved analog performance
• Specific power supplies
• Application specific connectors
• More flexibility in clocking, triggering
• Tighter integration of functions with DSP
• FPGA back-end allows for customization
• Improved data flows
• 300 MB/s IO transfer rates
• Improved DMA support
• Improved PCI streaming performance
• Pismo Toolset
• DSP BIOS supported
• DMA-driven IO leaves CPU free for calculations
• IO drivers significantly reduce complexity of
  programming

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671x Cache Controller

• Cache controller holds recently used data and
  program memory for faster access
• Controller allows the DSP to more efficiently use
  memory
• L2 cache allocation is defined by the user
• Algorithms may tune cache config to expected use
• Application programs benefit whether they need
  more data or program cache
• TI benchmarks show that the cache controller
  achieves 90 efficiency of a processor with
  infinite internal memory

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Efficient Bus Utilization

• High-performance FIFO interfaces to the DSP
• PCI bus requires minimum CPU intervention
• DMA channels easily all IO functions
• I/O channels require minimum CPU intervention
• DMA used for all transfers
• Burst register interface augments DMA One
  interrupt per burst move
• Reduces load on CPU to near 0

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Performance Metrics

• IO data to/from SDRAM bus usage calculation
• FIFO to DMA Controller 22.6 MB/s
• DMA Controller to SDRAM 22.6 MB/s
• Total bus usage 45.2 MB/s
• Bus usage as a percentage 15 (45.2/300 .15)

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Matador PCI Interface
FPGA
WR FIFO 256x64
PCI BM control
EMIF
DSP
RD FIFO 256x64
PCI 64/32 3V/5V
PCI interface
Registers
PCI target control
Controls

• 64-bit 3V/5V busmastering and slave PCI interface
• 300 MB/s burst rate from PCI FIFO to the DSP
• Programmable level controls and burst length for
  DMA interrupts
• Typical sustained performance is 80 MB/s under
  Win2K
• Bus-master performance is dominated by
  motherboard chipset

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Matador PCI Mailboxes

• 16 mailboxes in each direction are used for
  messaging system
• Software layer provides convenient means to make
  lower rate message channels
• Message channels are 60 kB/sec data rates for
  control and coordination
• Software driver manages low-level handling of
  mailboxes

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FIFOPort

• FIFOPort
• 16 bit parallel interface
• Transmit 80 M Bytes/sec (sustained DMA)
• Receive 80 M Bytes/sec (sustained DMA)
• Compatible with FIFOPort on existing C6x cards
  and ChicoPlus
• Facilitates inter-processor communications or
  peripheral expansion

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Triggering Basics

• Data collection done using a start, stop and
  timebase
• All trigger inputs software selectable for
  polarity and edge/level sensitivity

start
stop
timebase
Trigger Active Region
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Triggering

• Brackets when sampling will be performed

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Clock Sources

• When to sample once trigger is active
• DDS
• External TTL signal
• DSP timer 0/1
• SyncLink 0/1
• ClockLink

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Trigger Sources

• Start and Stop triggers are software selected
• Pulse or level with specified polarity on
• External, SyncLink, ClockLink
• Software
• Frame counter ( samples/frame)
• Frame timer ( microseconds/frame)
• Analog threshold (gt counts for N samples, A/D
  only)

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Trigger Modes

• Single-shot or continuous
• Single shot Single event capture
• DSP must re-arm the trigger
• Continuous Multiple event capture
• Retrigger each time start condition is met

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Capturing Frames of Data

• Limits data capture to a defined time period or
  number of points
• Framed acquisitions allow the capture of either N
  points, or capture all points in T period
• Periodic or aperiodic signals supported
• Example FFT is N points
• Timebase sample rate
• Stop trigger is N points after start

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Framed Data Capture
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Analog Threshold Monitoring

• When an analog channel exceeds or goes under a
  threshold, a trigger is fired for start or stop
• In this mode, the A/Ds are always sampling, but
  do not get stored until a start trigger is
  received
• Any enabled channel may be used as the trigger
  source
• Four sample hysterisis prevents false triggering
• Example capture N points after a threshold is
  reached from external source with external
• Start trigger threshold exceeded
• Timebase external
• Stop trigger after N points

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Analog Threshold Data Capture
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Alert Logging

• Alerts signify important times in data logging
  such as start time, stop time and overranges
• Alerts that may be logged
• start and stop triggers
• overranges
• over/under flow
• user events
• User Alerts allow the DSP to timestamp various
  events in the system
• Alert timestamp is 100 ns per tick, 32-bit length
• FIFO holds 85 Alerts

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Using Matador for Servo Control Applications

• Servo applications are most stringent real-time
  applications
• Data latency causes poor servo performance or
  instability
• Toro, Conejo and Oruga feature low latency
  converters and data paths specially selected for
  servo applications
• DAC servo timebase allows application to tune
  itself for servo calculation time

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Servo Control Timebase

• Servo Timing is controlled for consistent loops
• Removes requirements on software timing

A/D conversion
Your servo code
D/A conversion
t1
Calculation time
t2
t1t2 calculation time
Servo cycle period
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Matador Digital Error Correction

• All data is corrected for gain and bias errors
  real-time in the FPGA
• More stable over time and operating conditions
• Coefficients are stored in on-card ROM
• Programmed at factory test, field updatable

FPGA
A/D or DAC
Saturation logic
multiplier
FIFO
adder
Bias coefficient Memory
Gain coefficient Memory
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Developing Logic Applications for Matador Cards

• Every Matador card has two Xilinx Spartan2, 200K
  gate FPGAs
• Matador core PCI, clock steering, FIFOPort,
  32-bits digital IO, interrupt controls
• Analog IO interface FIFOs, error correction,
  triggering, A/D and DAC interfaces
• Each device may be customized for
  application-specific features
• Most logic devices have 25 to 50 free logic as
  delivered
• Source available under NDA for specific projects
• Contact Jean for NDA forms

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Custom Matador Applications

• Toro
• Automation Equipment
• Quadrature encoder interface for motion control
  application
• Conejo
• Materials testing application
• High speed stimulus-response measurement
• Delfin
• Power meter reading application
• Zero-crossing detectors with time stamped events

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Matador Logic Customization

• VHDL Source code
• Delivered as a Xilinx ISE project
• Includes constraints files and project control
  files
• VHDL Test bench provided
• ModelSim project files
• Many applications delete unneeded functions to
  free up more space and remove clutter