Withindie Process Variations:

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Within-die Process Variations How Accurately
Can They Be Statistically Modeled?
Wed Jan 23rd, ASPDAC08
Brendan Hargreaves Division of Engineering Brown
University Providence, RI 02912
Henrik Hult Division of Mathematics Brown
University Providence, RI 02912
Sherief Reda Division of Engineering Brown
University Providence, RI 02912
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Introduction to process variations

• Reasons for presence of process variations
• Inability to robustly print features sizes ?
  130nm
• Inability to precisely control the profile of the
  dopants

• Manifestation of process variations
• In devices dopant fluctuations/profile, gate
  length variations, LER
• In interconnects litho-induced spatial
  variations, CMP induced (dishing, erosion)

Inter-die process variations
Intra-die (within-die) process variations
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Impact of process variations
Process variations impact key electrical
parameters (delay and power) of ICs ? loss in
parametric yield and revenues of ICs
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Recent work on within-die process variation
modeling

• Friedberg and others (ISQED05)
• piece-wise linear correlation models and tested
  on 35 chips
• Bhardwaj and others (DAC06)
• Linear exponential models no testing on chips
• Xiong and others (ISPD06)
• exponential and generic model
• nonlinear optimization to calculate the model
  parameters
• no testing on chips
• Liu (DAC07)
• linear and exponential correlation models
• generalized least square fitting
• tested on 1 chip
• used variograms and kriging predictor to verify
  statistical accuracy

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Objectives of this work

• Design a scalable process variation extraction
  circuitry. Implement it and measure the process
  variation from silicon chips in an economical
  fashion.
• Use statistical techniques to analyze and model
  the measured process variation data. Verify the
  accuracy of the analysis.
• Develop techniques that generate synthetic
  process variation patterns that mimic the
  measured data.

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A. vMeter A scalable economical system for
process variation extraction
a ring oscillator block
example of measurements (chip 1)
RO period (ns)
vertical location
horizontal location
a scan chain of ring oscillator blocks
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A. vMeter tuning

• Only one RO is enabled at a time ? minimize the
  load and noise on power supply network
• Scan chains are interleaved ? minimize the
  propagation from RO to the frequency counter
• Scan chain is constructed in two orientations
  (left to right and right to left) and the results
  are averaged despite almost negligible difference
• Tile size is tuned to minimize the measurement
  noise and reduce measurement time

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B. Statistical analysis Introduction to
random fields
The measurement from a RO at a location l1 can be
considered a random variable D(l1)
The measurement from a RO at a location l2 can be
considered a random variable D(l2)

• The collection of random variables form a random
  field where the variables can be indexed by their
  spatial location
• Is there correlation between the different random
  variables in the field?
• We assume the random field is stationary,
  isotropic Gaussian field
• variance ?2 of the random variable does not
  depend on the location
• covariance between between two locations (l1,
  l2) depend only the distance between them

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B. Representing the correlations of a random field
covariance function
correlation function
scale parameter
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B. Examples of field correlations
Correlation between ROs as a function of distance
between them (chip 1)
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3
2
1
7
8
5
6
11
12
9
10
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B. Proposed statistical modeling methodology

• Choose an appropriate correlation function model.
  
• Calculate the model parameters using
  maximum-likelihood estimation from the
  measurement data.
• Verify the accuracy of the model using
  Kolmogorov-Smirnov test and variograms.

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B.I. Specifying correlation functions to model
within-die process variations
Exponential model
Matérn model
is the lag or the distance between the two ROs
is the modified Bessel function of the second
kind of order
is the Gamma function

• The Matérn model is a generic model that reduces
  to
• a linear model
• a exponential model
• a Gaussian model

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B.II. Model parameter estimation using maximum
likelihood estimation

• Choose an appropriate correlation model
  (exponential or Matern)
• Find the model parameters
  that makes sampling D from is
  as likely as possible

Maximizing the likelihood can be expressed solely
as a function of ? search for the model
parameters that maximize the
likelihood
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B.III Model verification using residual analysis

• Choose a model (exponential or Matérn)
• Use MLE to calculate the model parameters

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B.III Model verification using variograms

• Variograms are a popular analysis tool in spatial
  statistics. It has been also suggested in the
  context of within-die process variation F.
  Liu07

• The sample variogram based on the observations of
  the random field can be computed as follows

where Nh is the number of location pairs that are
at a distance h
variogram based on Matérn model
sample variogram based on observed data
variogram based on exponential model
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C. Synthetic generation of within-die variations

• Objective generate synthetic variation data that
  mimic silicon measurements
• Why needed? Useful for generating test cases and
  benchmarking purposes or creating large samples
• Basic idea
• Choose a correlation model (exp or Matérn) with
  some appropriate parameters. Construct the
  covariance matrix ? accodingly.
• Let ?AAT be the Cholesky decomposition of ?.
• Generate a random vector W of independent N(0, 1)
  variables
• Convert the random uncorrelated variables to
  correlated ones using the chosen model VAW.
• Scale appropriately D µsV

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Experimental setup

• Ten sample chips Altera Cyclone II FPGA EP2C35
  devices.
• All chips are manufactured with 90nm technology
  and all belong the same speed bin (fastest speed
  bin C6)

Floorplan
Each block can hold a chain of 16 inverters
35 rows
53 columns

• Each RO is enabled and sampled for 10ms

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EXP 1 Impact of RO tile size
RO Size 22 blocks (63 inverters)
RO Size 1 block (15 inverters)
RO Size 33 blocks (143 inverters)
RO Size 44 blocks (255 inverters)

• A tile size of 33 removes the unwanted
  measurement noise and cut down the process
  variation extraction time

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EXP 2 Results from 10 sample chips

• Patterns are similar to reported figures in
  literature, but produced economically using FPGAs
• Magnitude of inter-die variations is 15
• Magnitude of within-die variations is 3

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EXP 3 Statistical analysis of measured data
Objective Is the Gaussian random field model
reasonable? Can it capture the structure of the
spatial correlations?
construct variograms of the 10 chips
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EXP 4 Fitting the models to silicon data

• The results of the Kolmogorov-Smirnov test are
  very close to zero which validates the accuracy
  of our proposed modeling technique

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EXP 4 Analysis using variograms
variograms for four sample chips
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EXP 5 Generation of synthetic variation data
Examples of variation maps of synthetic chips
using the proposed model Can you visually notice
any difference from the real data? Useful can be
used for benchmarking and constructing test cases
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Contributions of this work

• Provided a complete treatment from test structure
  implement and process variation measurements to
  statistical modeling and analysis
• Proposed statistical modeling using exponential
  and Matern functions and used MLE for parameter
  estimation
• Verified our results using residual analysis and
  variograms on 10 sample chips
• Provided a method to generate synthetic
  within-die variation pattern that mimic
  observation data ? Useful for benchmarking and
  other related experiments
• Data and scripts are available for other
  researches at http//ic.engin.brown.edu/tools