Hardware Implementation

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Hardware Implementation

• Lecture B17

Lecture notes section B17
2
Last time

• Analysis of translation
• Writing efficient C

3
In this lecture

• Gates
• Combinatorial logic
• adder
• ALU
• Sequential logic
• flip-flop
• memory
• CPU
• fetch-decode-execute cycle

4
How to make a computer

• Computers are electronic equipment
• contain many connected electronic components
• memory
• Central Processing Unit (CPU)
• specialized devices (network, video, etc.)
• components largely made of circuits containing
  wires and gates

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Gates

• Tiny electronic switches
• made of transistors
• implement Boolean logic
• 0/1 ? low/high voltage
• digital
• for given inputs, produce known output
• according to truth table
• represented in circuit diagrams by symbols

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Gates
AND
NOT
OR
XOR
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Combinatorial logic

• What about more complex truth tables?
• Made by combining many gates together
• wires connect inputs and outputs
• each wire can carry only one bit, 0 or 1

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Combinatorial logic

• Circuits made from collections of gates
• outputs depend only on inputs
• not on prior state
• characterized by truth table
• comparable to Boolean expression

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Combinatorial logic
boolean expression
X (A B) (B C)
truth table
logic circuit
0
0
0
0
1
1
1
1
1
all three of forms are equivalent each can be
converted to the other two.
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Combinatorial logic

• Many parts of a computer are constructed of
  combinatorial logic
• adder circuit
• performs addition
• arithmetic logic unit (ALU)
• performs many kinds of arithmetic and bitwise
  logical operations
• contains adder circuit
• multiplexer and decoder
• direct bit traffic between components

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Adder

• A combinatorial circuit that adds binary values
• according to this truth table

Carry is equivalent to AND
Sum is equivalent to XOR
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Adder
Carry
In 1
In 2
Sum
This circuit can add two binary digits and is
called a half-adder
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Adder
Why half-adder. . . ?
1
1
9
. . . because to add multi-digit numbers each
column requires two additions
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Full adder
in 1
This circuit is called a full adder and can add
three binary digits
in 2
carry out
carry in
This OR gate combines the carries from the two
half-adders
sum
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Ripple-carry adder
A0
A1
A2
A3
B0
B1
B2
B3
out3
out2
out1
out0
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Ripple-carry adder
A0
A1
A2
A3
0101 0110 1011
B0
B1
B2
B3
0
0
1
0
1
0
0
0
0
1
0
0
0
1
1
0
1
out3
out2
out1
out0
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Ripple-carry adder

• So named because gate results (including carries)
  propagate (ripple) from LSB to MSB
• right to left
• corresponds to how humans add numbers with pen
  and paper
• More sophisticated, faster, adder circuits exist
  that can create the higher order carries more
  quickly

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Adder
A3-A0
B3-B0
Adders (and other arithmetic circuits) are
usually drawn like this in block diagrams
inputs

output
collections of parallel, related wires like this
are known as buses they carry multi-bit values
between components
out3-out0
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Arithmetic

• Computers need to do more than just addition
• arithmetic /
• logic ltlt gtgt
• Need a circuit that can select operation to
  perform

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Arithmetic Logic Unit (ALU)
A
B
more operations here
. . .
op 0
op 1
op 2
op 3



ltlt
Multiplexer a combinatorial circuit which
selects exactly one input
0
1
2
3
..
MUX
op
op selects operation 0 add, 1 multiply, ...
out
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Arithmetic Logic Unit (ALU)
A 15
B 2
for example compute 15 ltlt 2
more operations here
. . .
op 0
op 1
op 2
op 3



ltlt
other results also computed but ignored by
multiplexer
0
1
2
3
..
MUX
op 3
out 60
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Memory

• Computers need memory for storage
• Different kinds of memory distinguished by speed,
  size, cost and proximity to CPU
• main memory
• slowish, huge, cheap, far from CPU
• typical size 109 bits
• cache
• fast, medium-sized, expensive, near to CPU
• typical size 106 bits
• registers
• extremely fast, tiny, very expensive, located on
  CPU
• in MIPS (32 GPRs)32 bits 1024 bits

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Memory

• The smallest piece of memory is a single binary
  digit (bit)
• can hold 0 or 1 only
• A one-bit memory is called a flip-flop or a data
  latch
• because its value can flip and flop between 0 and
  1
• because it can latch onto a data value and store
  it

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Flip-flop

• Flip-flop needs two operation modes
• write store (memorize) a value
• read load (recall) a previously stored value
• Also need
• data in
• for telling flip-flop what value to store (0 or
  1)
• used only when writing
• data out
• for finding out what value flip-flop currently
  contains (0 or 1)
• used only when reading

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Flip-flop

• Flip-flop can be implemented with gates
• Not combinatorial logic
• because current output may depend on previous
  state
• Example of sequential logic
• current output depends on inputs and prior output

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Flip-flop
NOR gate OR gate followed by NOT gate
data in
data out
read/write
read/write control 0 read, 1 write
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Flip-flop writing
Try changing data in to 0 and watch data out
data in 1
1
1
0
1
1
0
1
0
1
0
data out 1
1
when read/write 1, data out data in
read/write 1 (write)
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Flip-flop reading
data in ?
?
0
0
0
1
0
?
?
1
0
data out 1
0
read/write 0 (read)
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Flip-flop
D data in
Q data out
Flip-flops are often drawn like this in block
diagrams
D
Q
CK
CK is read/write (clock because this input is
often connected to computers processor clock)
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Memory

• Memory can store many bits independently
• many flip-flops
• Need to identify which bit (flip-flop) to read or
  write
• Give each flip-flop a unique number (address)

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Memory
Decoder feeds input to selected output, 0 to all
others
data in
D
Q
address 0
CK
D
Q
data out
0
0
address 1
rd/wr
1
1
CK
MUX
DEC
2
2
3
3
D
Q
...
...
address 2
CK
D
Q
address
address 3
CK
. . . millions more flip-flops . . .
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Memory writing
Writing value 1 to flip-flop at address 2
data in
?
D
Q
1
address 0
0
CK
?
D
Q
data out
0
0
address 1
rd/wr
0
1
1
CK
MUX
DEC
2
2
1
1
3
3
D
Q
1
...
...
address 2
1
CK
?
D
Q
address
address 3
0
CK
2
. . . millions more flip-flops . . .
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Memory reading
Reading value from flip-flop at address 2
data in
D
Q
address 0
0
CK
D
Q
data out
0
0
address 1
rd/wr
0
1
1
CK
MUX
DEC
2
2
0
1
1
3
3
D
Q
1
...
...
address 2
0
CK
D
Q
address
address 3
0
CK
2
. . . millions more flip-flops . . .
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Memory

• Memory usually operates in terms of bytes (8
  bits), not single bits
• Repeat memory circuit eight times
• connect each memory circuit to one of the eight
  lanes of the data bus
• reads and writes occur in parallel for each bit
  in byte

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Central Processing Unit (CPU)

• Coordinates all computers components according
  to program being run
• Contains
• registers
• ALU
• program counter (PC)
• address of current instruction
• instruction register (IR)
• copy of current instruction
• control logic
• Runs programs using fetch-(decode)-execute cycle

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CPU
Registers
IR
out
Memory
in
Control logic
rd/wr
addr
ALU
PC
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Fetch-execute cycle fetch
Registers
IR
out
Memory
Stage 1 of fetch-execute cycle instruction at
address pointed to by PC is fetched into IR
in
Control logic
rd/wr
addr
ALU
PC
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Fetch-execute cycle decode
Registers
IR
out
Memory
Stage 2 of fetch-execute cycle instruction (now
in IR) is decoded by control logic to determine
which operation to perform
in
Control logic
rd/wr
addr
ALU
PC
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Fetch-execute cycle execute
Registers
IR
out
Stage 3 of fetch-execute cycle CPU performs the
operation (for example, arithmetic on two
registers)
Memory
in
Control logic
rd/wr
addr
ALU
PC
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Fetch-execute cycle update PC
Registers
IR
out
Memory
Stage 4 of fetch-execute cycle PCs value is
updated to point to the next instruction
in
Control logic
rd/wr
addr
ALU
PC
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Covered in this lecture

• Gates
• Combinatorial logic
• adder
• ALU
• Sequential logic
• flip-flop
• memory
• CPU
• fetch-decode-execute cycle

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Going further

• Digital logic
• CSE1308/CSE2306
• Next time
• Revision