EET 3350 Digital Systems Design

1
EET 3350Digital Systems Design
VHDL Behavioral Structural

• Dan Solarek

2
VHDL Concepts

• Entity and Architecture similar to symbol and
  schematic views of a logic circuit

3
VHDL Example

• Entity declaration for the 2 to 1 MUX

ENTITY mux2_1 IS PORT (in0, in1, sel IN
STD_LOGIC yout OUT
STD_LOGIC) END mux2_1
4
VHDL Example

• Logic circuit for a 2-1 MUX device
• Helpful for understanding architecture

In1
sel
yout
In0
5
VHDL Example

• Behavioral architecture for the 2 to 1 MUX

In1
sel
yout
In0
ARCHITECTURE a1 OF mux2_1 IS P1 PROCESS (sel,
in0, in1) BEGIN IF (sel 0) THEN yout
lt in0 ELSE yout lt in1 END IF
END P1 END a1
6
VHDL Example

• Structural architecture for the 2 to 1 MUX

In1
U2
sel
U4
U3
yout
U1
In0
ARCHITECTURE a2 OF mux2_1 IS SIGNAL sel_not,
in0_and, in1_and STD_LOGIC COMPONENT OR_GATE
PORT(x,y IN STD_LOGIC z OUT STD_LOGIC)
COMPONENT AND_GATE PORT (x,y IN STD_LOGIC z
OUT STD_LOGIC) COMPONENT INV_GATE PORT (x IN
STD_LOGIC z OUT STD_LOGIC) BEGIN U1
AND_GATE PORT MAP (in0, sel_not, in0_and) U2
AND_GATE PORT MAP (in1, sel, in1_and) U3
INV_GATE PORT MAP (sel, sel_not) U4 OR_GATE
PORT MAP (in0_and, in1_and, yout) END a2
7
VHDL Example

• Dataflow architecture for the 2 to 1 MUX

In1
sel
yout
In0
ARCHITECTURE a3 OF mux2_1 IS BEGIN yout lt
((in0 AND NOT(sel)) OR (in1 AND sel)) END a3
8
Configuration for 2 to 1 MUX

• bbbb

CONFIGURATION mux_behav OF mux2_1 IS FOR
a1 END FOR END mux_behav
9
Half Adder Circuit

• Looking at the truth table for a half adder, it
  is easy to visualize the circuit

10
Full Adder Circuit

• The circuit at right shows a full adder
  constructed from two half adders.
• XOR generates the sum output
• AND generates the carry output

half adder
half adder
11
Full Adder Entity Architecture
-- Dataflow model for a full adder circuit--
Library Statement declares the standard ieee
synthesis library LIBRARY ieee         USE
ieee.std_logic_1164.ALL-- Entity declares the
inputs and outputs using a PORT statementENTITY
fulladder IS PORT(Ain, Bin, Cin  IN STD_LOGIC
Cout, Sout  OUT STD_LOGIC)END
fulladder-- Architecture defines the function
or entity-- In this case the function is defined
using Boolean equationsARCHITECTURE dataflow OF
fulladder ISBEGIN -- Concurrent Signal
Assignment Statements Sout lt Ain XOR Bin XOR
Cin Cout lt (Ain AND Bin) OR (Ain AND Cin) OR
(Bin AND Cin)END dataflow
12
Full Adder - Architecture
-- In this case the function is defined by a
circuit structureARCHITECTURE structural OF
fulladder IS COMPONENT AND2  PORT( A, B IN
STD_LOGIC F OUT STD_LOGIC)END COMPONENT
COMPONENT OR3  PORT( A, B, C IN STD_LOGIC
F OUT STD_LOGIC)END COMPONENT COMPONENT
XOR2  PORT( A, B IN STD_LOGIC F OUT
STD_LOGIC)END COMPONENT SIGNAL AXB, AB, BC,
AC STD_LOGIC BEGIN F1 XOR2 port map (Ain,
Bin, AXB)       F2 XOR2 port map (AXB, Cin,
Sout)      F3 AND2 port map (Ain, Bin,
AB)      --Port Map Statements F4 AND2 port
map (Bin, Cin, BC) F5 AND2 port map (Ain, Cin,
AC) F6 OR3 port map (AB, BC, AC, Cout) END
structural
13
Binary Addition 4-Bit Numbers

• The following example illustrates the addition of
  two 4-bit numbers A(A3A2A1A0) and B(B3B2B1B0)

How would this change for a BCD adder?
14
Binary Addition 4-Bit Numbers

• The addition can be split-up in bit slices
• Each slice performs the addition of the bits Ai,
  Bi and the Carry-in bit Ci
• Ci lt carry-out bit of the previous slice
• Each slice is simply a full adder

15
4-Bit Binary Adder

• Circuit for a 4-bit parallel binary adder
  constructed from full adder building blocks

16
4-Bit Adder - Entity
LIBRARY ieee USE ieee.std_logic_1164.ALL --
VHDL model of a 4-bit adder constructed from four
full adders ENTITY four_bit_adder_st IS PORT (A,
B IN STD_LOGIC_VECTOR(3 downto 0) SUM
OUT STD_LOGIC_VECTOR(3 downto 0) CIN IN
STD_LOGIC COUT OUT STD_LOGIC) END
four_bit_adder_st
Cin
Cout
17
4-Bit Adder Structural
-- The architecture in this case is a structural
one ARCHITECTURE structural OF four_bit_adder_st
IS -- First all the components are declared. The
full adder is -- declared only once, even though
it will be used 4 times. COMPONENT fulladder
PORT(Ain, Bin, Cin  IN STD_LOGIC  
      Cout, Sout  OUT STD_LOGIC) END COMPONENT
-- The full adders are connected by carry
signals. These must -- be declared also.       
SIGNAL C STD_LOGIC_VECTOR(1 to 3) -- Port
map statements are used to define full adder
instances -- and how they are connected.        
BEGIN        F1 fulladder port map
(A(0),B(0),CIN,C(1),SUM(0)) F2 fulladder port
map (A(1),B(1),C(1),C(2),SUM(1)) F3 fulladder
port map (A(2),B(2),C(2),C(3),SUM(2)) F4
fulladder port map (A(3),B(3),C(3),COUT,SUM(3)) E
ND structural
18
4-Bit Adder Structural
-- The architecture in this case is a dataflow
one ARCHITECTURE dataflow OF four_bit_add_df
IS -- Again there will be internal carry signals
that are not -- inputs or outputs. These must be
declared as signals. SIGNAL C
STD_LOGIC_VECTOR(1 to 3) -- Concurrent signal
assignments can be used to describe -- each of
the 4 outputs and the carry signals. BEGIN
SUM(0) lt A(0) XOR B(0) XOR Cin C(1) lt (A(0)
AND B(0)) OR (A(0) AND Cin) OR (B(0) AND Cin)
SUM(1) lt A(1) XOR B(1) XOR C(1) C(2) lt (A(1)
AND B(1)) OR (A(1) AND C(1)) OR (B(1) AND
C(1)) SUM(2) lt A(2) XOR B(2) XOR C(2)
C(3) lt (A(2) AND B(2)) OR (A(2) AND C(2)) OR
(B(2) AND C(2)) SUM(3) lt A(3) XOR B(3) XOR
C(3) COUT lt (A(3) AND B(3)) OR (A(3) AND
C(3)) OR (B(3) AND C(3)) END dataflow