COCO F02 Class 15

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COCO F02- Class 15
Realizing Circuits with Different Kinds of
Flip-Flops Characteristic Equations Next State
Tables Excitation tables Design Procedure Kinds
of Registers and Counters Storage
Registers Shift Registers Counters Resetting
Counters
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COCO F02- Class 15
Implementation with Different Types of
Flip-Flops Ripple Counters This material is
from last years textbook, Katz, Section 6.3,
7.1.1 thru 7.1.3, 7.3.2, 7.4, 7.5.1 (We mostly
like Wakerly better, but like these sections of
Katz more.)
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Different Flip-Flops
There are 4 types of flip-flops R-S, J-K, D, T

• R-S latch has only a few applications D latch is
  widely used (e.g., in registers, memories).
• J-K vs D flip-flops
• a given design usually uses fewer flip-flops with
  J-Ks than with Ds.
• J-Ks have 2 inputs each, so use more wires.
• VLSI wires more expensive than gates.
• Therefore Ds are most common.
• T flip-flops
• easy to construct, never seen as a chip
• useful in counters.

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Characteristic Equations
Q is the current state, Q is the next state

• The characteristic equation tells you what effect
  the inputs have on the flip-flop
• R-S latch Q S R' Q
• D F/F Q D
• J-K F/F Q J Q' K' Q
• T F/F Q T Q' T' Q

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Next State Tables

• We know the flip-flops current state, and its
  inputs.
• What is its next state?

0 1 1 0
0 1 0 0 1 1 X X
0 1 0 0 1 1 1 0
0 0 1 1
X that input is illegal
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Excitation Tables
Suppose we wanted to change from state Q to state
Q for example, from Q 1 to Q 0
X 1
1 0
RESET or TOGGLE
What should be the input (excitation) for a T
flip-flop or a D flip-flop to make this change?
J-K flip-flop
Why is JK X1? Because either JK 01 or JK 11
will change state 1 to state 0. Similar reasoning
yields the other entries.
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In-class Exercise
Fill in the rest of the table
Q Q R S J K T D 0 0 0 1 1 0 X 1 1 0 1 1
Answer
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Answer
The rest of the table filled in
Q Q R S J K T D 0 0 X 0 0 X 0 0 0 1 0 1 1 X 1 1 1
0 1 0 X 1 1 0 1 1 0 X X 0 0 1
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Example

• We control a traffic light with a J-K F/F. It is
  0 if the north-south light is red, or 1 for
  green.
• What must the input be to switch the light from
  red to green?

Answer J1, KX.
Our timer (or whatever) must generate this at the
appropriate time. Since K is a dont care, pick K
0 or K 1 depending on which makes the design
simpler.
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Design Example
Convert a D flip-flop into a T flip-flop
1. Begin by writing out the Next State Table for
the desired transitions that is, fill in the
Next StateTable for the T flip-flop. 2. Next fill
in the Flip-Flop Inputs for the given flip-flop
using its Excitation Table to obtain the desired
transitions that is, list the inputs to the D
flip-flop that will change the current state to
the next state. 3. Finally, using the current
inputs and current state, find the minimized
expression for the combinational network to
realize the given flip-flop inputs. The table
for this problem is given on the next slide.
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Table for Design Example
Step 1.
Step 2.
Step 3.
D T Q' T' Q T ? Q
0 1 1 0
0 1 1 0
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Sequential Logic Components

• Flipflops most primitive "packaged" sequential
  circuits
• More complex sequential building blocks
• Storage registers, Shift registers, Counters
• Available as components in the TTL Catalog
• Registers
• Store a word (4 to 64 bits)
• E.g. Pentium has several registers
• Counters
• Count thru a sequence of states
• E.g., the seconds display on a clock.
• Both of these have many variations.

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Flip-Flops in LogicWorks

• LW has JK F/Fs called the (a) JK F/F, or (b) JK
  F/F non-inverting.
• They have asynchronous R (reset) and S (set)
  inputs.
• C is the clock.
• The Qs change on the falling clock edge (negative
  edge triggered).
• When R and S are active, they override J, K and
  C.
• R and S are used to initialize the state of the
  F/F.
• If R and S are not active, then it operates as a
  JK F/F.

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Storage Registers

• Storage registers store data, without changing
  it.
• A D F/F is a 1-bit storage register.
• A Register File stores a group of words of data.
• You specify which word to read or write.
• A Random-Access Memory is like a large register
  file. It may store 32MB of data or more.

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Multibit Storage Registers
use D F/Fs in groups to make a multibit register
Clocks in 4 bits in parallel, or resets to 0.
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74171 Quadruple D F/F with Clear
Triangle indicates clock input No bubble
indicated positive edge triggered
The /CLR clears all 4 bits
This stores 4 bits in parallel
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Register Variants

• Sometimes theres also a LOAD input.
• When LOAD is false, the F/F doesnt change.
• When LOAD is true during the clock edge, the F/F
  updates itself.
• Sometimes the outputs are tri-state or open
  collector.
• This allows several registers to be connected to
  the same output wire

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74377 Octal D F/Fs with Enable
Positive edge triggered
... but only when /EN is active LO
Stores an 8 bit number
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74374 Octal D F/Fs with Tri-State Outputs
Positive edge triggered
Stores an 8 bit number
/OE is active LO output enable Determines when
register contents are visible at the outputs
Note LW uses different labels from the 377, and
from Katz!
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Register Files
Store several words

• You read or write one word at a time.
• 74670 4-by-4 Register File with Tri-State
  Outputs
• 4 words of 4 bits each
• Data in D0,D1,D2,D3 Data out Q0,Q1,Q2,Q3
• Read selects RB,RA Write selects WB,WA
• Active low read enable /GR, write enable /GW
• Can read and write simultaneously.
• No clock. Read or write when enables asserted.
• Watch out for glitches!

To write Word 1, set GW 0 and (WB, WA) to
(0,1) To read Word 2, set GR 0 and (RB, RA) to
(1,0)
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Random Access Memories

• Same idea as a register file, but optimized for
  very many words.
• Small RAM 256 4-bit words.
• Large RAM 4 million 8-bit words.
• More details later.

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Shift Registers

• Some registers are designed to change their
  stored data.
• Shift registers shift their bits left or right.
• For example, right shift
• Original contents 1000
• Shift right 0100
• Shift again 0010
• and again 0001
• once more, wrapping 1000
• Application send a word to a modem bit-by-bit.
• We need some way to initialize the shift register.

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Input and Output

• Serial input
• The shift register doesnt wrap around from right
  to left.
• Instead, the user provides the new leftmost bit.
• Parallel input
• You can specify the whole word at once.
• Serial output
• The bit just shifted off the right is visible at
  a pin.
• Parallel output
• Every stored bit is visible at an output pin.
• This uses more pins, which can be a problem.

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74194
4 bit bidirectional universal shift register
4 modes set by S1,S0 00 hold data
(QA,QB,QC,QD) 01 shift right (SR,QA,QB,QC) 10
shift left (QB,QC,QD,SL) 11 parallel load
SL (aka LSI) left shift input SR (aka RSI)
right shift input
Positive edge triggered
/CLR asynchronous clear
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74194 continued

• Notation conflicts
• LogicWorks uses SL, SR. Katz uses LSI, RSI.
• LW uses A,B,C,D for inputs and QA,QB,QC,QD for
  outputs.
• Motorola uses P0,P1,P2,P3 for inputs and
  Q0,Q1,Q2,Q3 for outputs.
• Note that the normal LW convention is that A is
  the lo-order bit. This is the way you normally
  connect the hex keyboard and the hex display.
  For the 194, A and QA are the hi-order bits. It's
  confusing.
• Right shift in more detail. All together on the
  rising clock
• SR ? QA, QA ? QB, QB ? QC, QC ? QD, QD is lost.
• Connecting QD to SR makes a circular shift
  register.
• Left shift in more detail.
• SL ? QD, QD ? QC, QC ? QB, QB ? QA, QA is lost.

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UART
Universal Asynchronous Receiver-Transmitter

• Application MODEM
• Transmit
• Reads a word in parallel from computer, then
  writes it, bit-by-bit to a serial data
  communications line.
• Receive
• Reads a word bit-by-bit from a serial line into a
  register, then the computer reads the word in
  parallel from it.

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Counters
steps thru a well-defined sequence of states

• An 3 bit up-counter counts up and wraps 000 ?
  001 ? 010 ? 011 ? 100 ? 101 ? 110 ? 111 ? 000 ?
  etc.
• A down-counter counts down.
• A binary counter counts in binary, like the
  above.
• A decade counter counts from 0 to 9 and wraps
• Sequence 0000 ? 0001 ? 0010 ? 0011 ? 0100 ? 0101
  ? 0110 ? 0111 ? 1000 ? 1001 ? 0000 ? etc.
• A clock might use 2 60-step counters and a
  12/24-step counter, to count the seconds,
  minutes, and hours.
• Another counter application washing machine
• Sequence fill with warm water, agitate, drain,
  spin, fill with cold water, agitate, drain, spin,
  stop.

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Gray Code Counters
Only one bit changes at a time as it steps
through all possible states

• A 4-bit Gray code counter will step thru 16
  states and repeat.
• This avoids glitches that might occur in the next
  circuit downstream if two counter bits are
  supposed to change together, but one changes
  slightly before the other.
• To produce a Gray code, imagine a 4-dimensional
  hypercube (or tesseract), with 16 vertices. A
  legal transition goes along an edge, since then
  only one bit changes.
• Visiting all 16 vertices of the tesseract,
  walking along the edges, produces a 4-bit Gray
  code.

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Ring Counters
A 4-bit ring counter has only 4 states

• Sequence 0001 ? 0010 ? 0100 ? 1000 and repeat.
• Why use it?
• The hardware is simpler.
• You need just a shift register with feedback,
  instead of implementing 4 boolean functions.

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Johnson (Mobius) Counters
has 8 states with 4 bits

• A Johnson counter is almost as simple as a ring
  counter (instead of 4 states with 4 bits).
• Sequence 1000 ? 1100 ? 1110 ? 1111 ? 0111 ? 0011
  ? 0001 ? 0000 and repeat.
• The trick is to complement the right bit before
  feeding it back into the left.
• This is also a Gray code sequence.

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74163
Synchronous 4 bit counter

• All operations occur on the rising clock edge.
• 4 data inputs D,C,B,A
• 4 control inputs
• P, T, /LOAD, /CLR
• 4 data outputs
• QD,QC,QB,QA
• 1 control output RCO
• /CLR clears the counter.
• /LOAD parallel loads it.

Note LW, and Katz use different labels from
Motorola for the 163!
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74163
Synchronous 4 bit counter

• P T 1 makes the counter count up by 1 (in
  binary, 0000 to 1111 and wrap around),
• P or T 0 makes the counter hold its value.
• RCO is the ripple carry out.
• Its asserted on the same cycle that the counter
  hits 1111.
• This lets you combine counters to count up to,
  say, 255 or 65535.

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Resetting Counters
Random power-up states
The counter may be in any possible state This may
include skipped states
In the counter example from the previous lecture,
states 001, 100, 111 were skipped It is
possible that the random power-up state may be
one of these Can we be sure the counter will
sequence properly?
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Don't-Care Assignments
K-map minimization
The Xs for the Toggle Inputs were set by the
K-maps to minimize the T Flip-Flop Input Functions
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Skipped State Behavior
Sequences from K-map minimization
When these K-map assignments are made for the Xs,
it results in 001 ? 100, 100 ? 111, and 111 ?
001
Therefore, the counter might not sequence properly
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Counter Reset Solution
Common methods used to reset flip-flops
Use a separate Reset input switch in the
circuit Use a resistor-capacitor (RC) network to
provide a signal that is held briefly while
circuit is powered up. This signal is used to
reset all flip-flops. After a few milliseconds,
the signal is de-asserted.
(Values can be assigned to the dont-care next
states to force the counter into the desired
state after a few clock events.)
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Implementation vs Flop-Flop Types
J-K, D or T flip-flops
A given State Transition Table (current
state-next state) can be implemented using any of
the 4 flip-flops types R-S, J-K, T, or D (the
R-S is a proper subset of the J-K, so we will
skip it - R-S F/Fs, like T F/Fs, are not
manufactured anyway) The appropriate Excitation
Table must be used in setting up the flip-flop
input function table The input functions must be
appropriate for the flip-flop type
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J-K Flip-Flops
3-bit Counter 0 ? 2 ? 3 ? 5 ? 6 ? 0
Present State
Next State
Flip-Flop Inputs
C B A C B A JC KC JB KB JA KA
0 X 1 X 0 X X X X X X X 0 X X 0 1 X
1 X X 1 X 0 X X X X X X X 0 1 X X
1 X 1 X 1 0 X X X X X X X
0 0 0 0 1 0 0 0 1 X X X 0 1 0 0 1 1 0
1 1 1 0 1 1 0 0 X X X 1 0 1 1 1 0 1 1 0
0 0 0 1 1 1 X X X
Flip-Flop Input Functions
Fill in flip-flop input functions based on J-K
excitation table
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Input Function K-Maps
A
A
1
A C
B C'
C
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J-K Flip-Flop Counter
3-bit Counter 0 ? 2 ? 3 ? 5 ? 6 ? 0
Resulting Logic Level Implementation 2
Gates, 10 Input Literals Flip-Flop Connections
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D Flip-Flop Input Functions
3-bit Counter 0 ? 2 ? 3 ? 5 ? 6 ? 0
Simplest Design Procedure D F/F inputs are
identical to the next state outputs in the state
transition table
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D Flip-Flop Counter
3-bit Counter 0 ? 2 ? 3 ? 5 ? 6 ? 0
Resulting Logic Level Implementation 3
Gates, 8 Input Literals Flip-Flop connections
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Comparison
3-bit Counter 0 ? 2 ? 3 ? 5 ? 6 ? 0

• T F/Fs well suited for straightforward binary
  counters
• But yielded worst gate and literal count for this
  example!
• J-K F/Fs yielded lowest gate count
• Tend to yield best choice for packaged logic
  where gate count is key
• D F/Fs yield simplest design procedure
• Best literal count
• D storage devices very transistor efficient in
  VLSI
• Best choice where area/literal count is the key

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Ripple Counters
Deceptively attractive alternative to synchronous
design style
Count signal ripples from left to right Why does
this work as a counter?
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Ripple Counter Behavior
State transitions are not sharp!
This simple design exhibits timing problems
similar to those caused by the delayed carry-out
in adders Also similar to adders, multibit
counters are created by cascading smaller 4 or 8
bit counters together
Can lead to "spiked outputs" from combinational
logic decoding the counter's state
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Asynchronous vs. Synchronous Counters
Cascaded Synchronous Counters with Ripple Carry
Outputs
First stage RCO enables second stage for counting
RCO asserted soon after stage enters state
1111 A function of the P T Enables Downstream
stages lag in their 1111 ? 0000
transitions Affects Count period and decoding
logic
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Homework
A. Convert an R-S flip-flop into a J-K
flip-flop. 1. Begin by writing out the Next State
Table for the desired transitions that is, fill
in the Next StateTable for the J-K
flip-flop. 2. Next fill in the Flip-Flop Inputs
for the given flip-flop using its Excitation
Table to obtain the desired transitions that is,
list the inputs to the R-S flip-flop that will
change the current state Q to the next state
Q. 3. Finally, using the current inputs J and K
and current state Q, find the minimized
expression for the combinational network to
realize the given flip-flop inputs R and S.
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B. Reverse engineer this circuit

• Redesign this circuit using D Flip-Flops.

Hand in Circuit for D F/F Counter