Circuit Characterization

1
Circuit Characterization
Feb 4, 2005
2
Basic Device Equations (p.51)

• Cutoff region Vgs ? Vt
• Ids 0
• Linear/non-saturation region 0ltVdsltVgs-Vt
• Ids ?((Vgs Vt)Vds Vds2/2)
• Due to Vds2/2, it is not really linear unless is
  Vds very small
• Saturation region 0ltVgs Vt ltVds
• Ids ?(Vgs Vt)2/2

3
Terms

• Ids is drain-to-source current
• Vds is drain-to-source voltage
• Vgs is gate-to-source voltage
• Vt is threshold voltage
• ? is MOS transistor gain factor
• ?(??/tox)(W/L), where ? is carrier mobility, ?
  is gate oxide permittivity, tox is thickness of
  gate oxide, W and L are gate width and length
• Example on p. 53

4
Importance of Interconnect

• Interconnect delay dominates gate delay

delay (ps)
technology
5
Wire Resistance

• Basic formula R(?/t)(l/w)
• ? resistivity
• t thickness, fixed for a given technology and
  layer number
• l conductor length
• w conductor witdh

l
t
w
6
Sheet Resistance

• Simply R(?/t)(l/w)Rs(l/w)
• Rs sheet resistance Ohms/square, where t is the
  metal thickness for that metal layer
• l conductor length
• w conductor witdh

l
w
7
Typical Rs (Ohm/sq)
Min Typical Max
M1, M2 0.05 0.07 0.1
M3, M4 0.03 0.04 0.05
Poly 15 20 30
Silicide 2 3 6
Diffusion 10 25 100
N-well 1000 2000 5000
8
Compute Resistance

• Partition long wire into rectangles
• Count the number of squares ((l1/w1)(l2/w2)(l3/w
  3))Rs

w2
l1
w1
l2
w3
l3
9
More Accurate Method
w1
w1
w2
Ratiow1/w2
w2
Ratio Rs
1 2.5
1.5 2.55
2 2.6
3 2.75
Ratio Rs
1.5 2.1
2 2.25
3 2.5
4 2.65
10
Contact and Via

• Fixed resistance for each type of contact and via
• 0.25 ohm to 10 ohms
• Could vary due to process variation

11
Capacitor

• A capacitor is a device that can store an
  electric charge by applying a voltage
• The capacitance is measured by the ratio of the
  charge stored to the applied voltage
• Capacitance is measured in Farads

12
3D Parasitic Capacitance

• Given a set of conductors, compute the
  capacitance between all pairs of conductors.

1V

-
-



-
CQ/V
-

-
-
-
13
2D Simplified Model

• Area capacitance area overlap between adjacent
  layers
• Coupling capacitance between side-walls on the
  same layer
• Fringing capacitance between side-wall and
  adjacent layers

m3
m2
m2
m2
m1
14
Wire Capacitance

• More difficult due to multiple layers, different
  dielectric, void, and conformal

?8.0
m3
void
m3
multiple dielectric
?4.0
m2
m2
conformal
m2
m2
m2
?3.9
?4.1
m1
m1
15
2D Method

• C Ca(overlap area)
• Cc(length of parallel run)
• Cf(perimeter)
• Coefficients Ca, Cc and Cf are given by the fab
• Cadence Dracula
• Fast but inaccurate

16
2.5D Method

• Consider interaction between layer i and layers
  i1, i2, i1 and i2
• Consider distance between conductors on the same
  layer
• Cadence Silicon Ensemble
• Accuracy ?50

17
Library Based Methods

• Build a library of tens of thousands of patterns
  and compute capacitance for each pattern
• Partition layout into blocks, and match with the
  library
• Accuracy ?20

18
3D Methods

• Finite difference/finite element method
• Most accurate, slowest
• Raphael
• Boundary element method
• FastCap, Hicap
• Monte Carlo random walk
• QuickCap