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Homework for Thursday, November 4

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Mode 1 devices are designed to 'talk' to each other ... A 'Write Port C' command can only change Port C pins configured in Mode 0, output ... – PowerPoint PPT presentation

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Title: Homework for Thursday, November 4


1
Homework for Thursday, November 4
  • Draw the connections between the 8255s and write
    8088 assembly language programs to have two
    computers communicate using 8255s.
  • Computer 1 should transmit using PortB as an
    output in Mode 1. Transmit 20 bytes of data from
    an array called DATAOUT (DATAOUT db
    ?,?,?,?,?,?,?,?)
  • Computer 2 should receive using PortA as an input
    in Mode 1. Store the 20 bytes received in an
    array called DATAIN (DATAIN db ?,?,?,?,?,?,?,?)

2
Read/Write HandshakingMode 1 devices are
designed to talk to each other
Tx
PortA (PC4) STBA (PC5) IBFA (Output) PC7
PortB OBFB (PC1) ACKB (PC2) PC5 (input)
Rx
How do you know the other computer is ready to
begin a transmission? One computer has to be
on, and wait for a signal from the other
computer that it is ready. This example has the
transmitting computer on waiting for a ready to
receive signal.
3
Read/Write HandshakingMode 1 devices are
designed to talk to each other
Tx
PortA (PC4) STBA (PC5) IBFA (Output) PC7
PortB OBFB (PC1) ACKB (PC2) PC3 (input)
Rx
SetupRX SetupTX Mov dx, stat2 mov dx,
stat2 Mov al, 10110???xb mov al, 1????101xb
Port A Mode 1 input Port B Mode 1output Port
CH output Port CL input out dx, al out
dx, al ret ret
4
TX program
Send20 jmp gt l1 DATAOUT db 20 dup (?) l1 Call
FillDataOut a procedure that generates the
data push ax, cx, dx, si Call SetupTX Port B
mode 1 output, cl input Mov dx, port2c l1 in al,
dx test al, 00001000xb jnz l1 wait for a
zero l2 in al, dx test al, 00001000xb jz l2
wait for high, positive edge initiates data
transfer
5
TX program
mov cx, 20 mov si, 0 l3 mov dx, port2b mov
al, Dataout Si out dx, al send one
byte, OBFb goes low, putting neg edge on
STBa inc si mov dx, port2c l4 in al,
dx test al, 00000010xb watch OBFb jz l4 as
long as OBFb is low, no edge on ACKb yet loop
l3 when OBFb goes high, send another byte pop
si, dx, cx, ax ret
6
RX program
Get20 jmp gt l1 DATAIN db 20 dup (?) l1 push ax,
cx, dx, si Call SetupRX Port B mode 1 output,
cl input Mov dx, stat2 mov al, 0???1110xb bit 7
set to 0 out dx, al mov al, 0???1111xb bit 7
set to 1 out dx, al positive edge to initiate
data transfer The ???s can be replaced with
any set of 1s and 0s
7
RX program
mov si, 0 mov dx, port2c l4 in al, dx test al,
00100000xb watch IBFa jz l4 as long as IBFa
is low, no edge on STBa yet l3 mov dx, port2a
high on IBFa means a byte is present in al,
dx IBFa falls low, sending neg edge to ACKb
mov DataIn Si ,al inc si cmp si,
20 jb l4 data stored in DATAIN (0 - 19) pop
si, dx, cx, ax end receiving when index 20 ret
8
Whats wrong with the RX program given?
  • No guarantee the IBFa is low prior to the 1st
    transition
  • Unless IBFa goes low when Port A is put in Mode 1
    input mode
  • Have to perform a test using an 8255 and an
    oscilloscope, voltmeter, or logic analyzer,or
    locate documentation

9
Use the INTRa and INTRb
In Mode 1, input, the INTRa line will go high
only when 1) it is enabled, AND, 2) it receives a
negative edge on STBa
To use INTRa 1) disable INTRa INTRa goes
low 2) enable INTRa INTRa stays low until a
neg edge on STBa
INTRa can be connected to an interrupt
controller and request an interrupt in hardware,
or INTRa can be unconnected and polled to
determine when new data is available
10
INTRa enable
PA7 - PA0
PC7
OBFa
PC6
INTEa
ACKa
PC3
INTRa
PC5, PC4
2
In Port A mode 1 input, PC6 is ACKa, an input Bit
Set/Reset to PC6 sets and clears the interrupt
enable bit, INTEa
11
Reading Ports configured as outputs
  • When Port A is programmed as an output, and then
    the Port is read, the value from Port A will
    represent the physical state fo the output pins,
    i.e., if an output pin is shorted to ground, the
    value read from Port A would always be 0,
    regardless of the value written.
  • Ports B and C, the value read represents the
    state of the output latch, not the physical state
    of the pins.

Taken from http//developer.intel.com/design/perip
hrl/overview/7190.html
12
Initial states of IBFx, OBFx
Port A All modes Output data is cleared,
input data is not cleared Port BMode 0 Output
data is cleared, input data is not clearedMode
1 Both input data and output data are
cleared Port CMode 0 Output data is cleared,
input data is not clearedMode 1 and Mode 2
IBFx and INTRx are cleared, OBFx is set Outputs
that are not used for handshaking are
cleared Spare inputs are not
affected Interrupts are disabled.
Taken from http//developer.intel.com/design/perip
hrl/overview/7190.html
13
Write Port C
  • A Write Port C command can only change Port C
    pins configured in Mode 0, output
  • When Port A is in Mode 1 or Mode 2, pins in Port
    C high must be accessed with the Set/Reset Port
    C Bit command (status word bit 7 0)
  • When Port B is in Mode 1, pins in Port C low must
    be accessed with the Set/Reset Port C Bit
    command (status word bit 7 0)
  • Any pins configured as outputs can be written
    using Set/Reset Port C Bit(OBFx, IBFx, INTRx).
    Pins configured as inputs are unaffected.

Taken from 82C55A CHMOS Programmable Peripheral
Interface, 1995, Intel
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