ECE 501

1
ECE 501

• Session 23
• Dr. John G. Weber
• KL-241E
• 229-3182
• John.Weber_at_notes.udayton.edu
• jweber-1_at_woh.rr.com
• http//academic.udayton.edu/JohnWeber

2
Full Adder Sample Design

• Consider adding two four-bit numbers, say 0101
  and 1001
• Looking at the example problem, we can build the
  following truth table for a single stage of the
  adder

0101 1001 1110
3
Full Adder Equations

• Using the minterm approach
• Sum abcin abcin abcin abcin
• Carry-out abcin abcin abcin abcin

4
Verilog HDL for Full Adder Module

• //fulladder.v
• //Full Adder Module using minterm equations
• module fulladder(a,b,cin, sum, cout)
• input a, b, cin
• output sum, cout
• assign sum !a !b cin !a b !cin
  a !b !cin a b cin
• assign cout !a b cin a !b cin
  a b !cin a b cin
• endmodule

5
Simulation Results for Full Adder Module
6
Behavioral Code Concept

• Previous example provides structural HDL which is
  one-to-one with the logic
• Can also specify the module by specifying its
  behavior

//fulladder_b module fulladder_b(a, b, cin,
sum, cout) input a, b, cin output sum,
cout assign cout, sum a b cin
//behavioral assignment endmodule
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Behavioral Simulation Results
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A Two-bit Ripple Carry Adder

• If we treat the Full Adder Module as a black box,
  we can use it to make multiple bit adders

9
Verilog HDL for Two-bit Ripple Carry Adder

• //add_2_r.v
• //Two-bit ripple carry adder example
• //Uses fulladder module
• module add_2_r(A, B, cin, SUM, cout1)
• input 10 A,B
• input cin
• output 10 SUM
• output cout1
• wire 10 A, B, SUM
• wire cin, cout1
• fulladder FA1(A1, B1, cout0, SUM1, cout1)
• fulladder FA0(A0, B0, cin, SUM0, cout0)
• endmodule

10
Assignment 1Due 9/1/2004

• Prove Theorems 1 through 4 algebraically.
• Show that theorems 5 and 6 are true by using a
  truth table.
• Read Chapters 1, 2, and 3 of the text
• Using structural code, develop a verilog module
  for the full adder discussed in class.
• Code and run examples from class using Quartus.
  (Do not turn in)

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Opening Quartus
12
Creating a Project
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Creating a Project (Cont)
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Creating a Project (Cont)
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Creating a Project (Cont)
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Creating a Project (Cont)
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Creating a Project (Cont)
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Creating a Project (Cont)
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Creating a Project (Cont)
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Project Created
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Creating Your Project File
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Creating Your Project File (cont)
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Creating Your Project File (cont)
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Creating Your Project File (cont)
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Compiling Your Project
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Verilog Language Elements

• Identifiers
• Any sequence of letters, digits, the character
  and the _(underscore)
• First letter must be character or _
• Identifiers are case sensitive
• Examples
• Count
• COUNT //Distinct from Count
• _R2_D2
• R56_67
• FIVE
• Escaped Identifier
• Provides a way to include any printable ASCII
  character in an identifier
• Starts with a \ and ends with white space (space,
  tab, newline)
• Examples
• \7400
• \..
• \
• \Q
• Notebackslash and terminating space not part of
  identifier

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Keywords

• Keywords are identifiers reserved by the language
• Keywords can only be used in certain contexts
• Keywords are lower case
• e.g. always is a keyword but ALWAYS is not
• Note an escaped keyword is distinct from the
  keyword
• e.g. \wire is not a keyword but wire is

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Keyword Table
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Keyword Table (cont)
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Comments

• Comments in Verilog similar to those in C
• Two forms
• Start comment with two slashes
• e.g. // this is a comment
• This form of comment ends at the end of the line
• Start Comment with / and end with /
• This form may extend over multiple lines
• e.g. / This comment
• extends across
• three lines. /

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Format

• Verilog is case sensitive
• Verilog is free form
• white space has no effect
• Example
• //add_2_r.v
• //Two-bit ripple carry adder example
• //Uses fulladder module
• module add_2_r(A, B, cin, SUM, cout1)
• input 10 A,B
• input cin
• output 10 SUM
• output cout1
• wire 10 A, B, SUM
• wire cin, cout1
• fulladder FA1(A1, B1, cout0, SUM1, cout1)
• fulladder FA0(A0, B0, cin, SUM0, cout0)
• endmodule

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Format (cont)
//add_2_r.v /Two-bit ripple carry adder example
Uses fulladder module / module add_2_r(A, B,
cin, SUM, cout1) input 10 A,B input cin
output 10 SUM output cout1 wire 10 A, B,
SUM wire cin, cout1 fulladder FA1(A1, B1,
cout0, SUM1, cout1) fulladder FA0(A0, B0,
cin, SUM0, cout0) endmodule
33
Compiler directives

• Identifiers that start with (backquote) are
  directives to the compiler
• Directive remains in effect throughout the
  compilation (spans files if necessary)
• Directives may be canceled by another directive
• Directives
• define, undef supported by Quartus
• ifdef, else, endif supported by Quartus
• include supported by Quartus
• default_nettype
• resetall
• timescale
• unconnected_drive, nounconnected_drive
• celldefine, endcelldefiine

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define and undef

• define
• Used for text substitution (like define in C)
• Example
• define MAX_BUS_SIZE 32
• .
• .
• .
• reg MAX_BUS_SIZE 1 0 AddReg
• undef
• removes definition of previously defined text
  macro
• Example
• undef MAX_BUS_SIZE

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Two-bit Ripple Adder Using define
//add_2_r.v //Two-bit ripple carry adder
example //Uses fulladder module define Word
2 module add_2_r(A, B, cin, SUM, cout1) input
Word-10 A,B input cin output Word-10
SUM output cout1 wire Word-10 A, B,
SUM wire cin, cout1 fulladder FA1(A1, B1,
cout0, SUM1, cout1) fulladder FA0(A0, B0,
cin, SUM0, cout0) endmodule
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ifdef, else, and endif

• Used for conditional compilation
• else is optional
• Example
• ifdef WINDOWS
• parameter WORD_SIZE 16
• else
• parameter WORD_SIZE 32
• endif

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include

• Includes the contents of any file in-line
• Can be specified with relative or complete path
  name
• Compiler replaces this line with contents of
  specified file
• Example
• include filename.v

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Other Compiler Directives(not available in
Quartus)

• default_nettype net keyword//specify net type
  for implicit declarations
• resetall //resets all compiler directives to
  their default values
• timescale time_unit/time_precision //specify
  delay times and precision
• unconnected_drive and nounconnected_drive
• Any unconnected input ports in module instances
  that appear between these two directives are
  pulled up or down
• Example unconnected_drive pull1
• .
• //unconnected ports pulled to 1
• nounconnected_drive
• celldefine and endcelldefine
• module declared between these two directives
  marked as a cell module

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Value Set

• Verilog HDL has following four basic values
• 0 logic-0 or false
• 1 logic-1 or true
• x unknown
• z high-impedance
• A Verilog constant is composed of the above
  values
• e.g. 0x1z

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Integers

• Two forms
• Simple Decimal
• e.g. 32 is decimal 32
• e.g. 15 is decimal 15 (twos complement form)
• Base format
• Specify the size, the base and the value
• size base value
• size is number of bits
• base is o or O for octal, b or B for binary, d or
  D for decimal, h or H for hexadecimal
• value is sequence of symbols from the base
• Examples
• 5 o37 5-bit octal
• 4 D2 4-bit decimal
• 4 b1x01 4-bit binary (note an underscore, in
  positions other than first, can be used to
  improve readability)
• 4 b1x_01 is same as above
• 8 h 2A is eight-bit hexadecimal
• Note spaces are allowed between size and and
  between base and value. No space is allowed
  between and base

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Reals and Strings (not supported in Quartus)

• Reals
• Decimal notation with numerals on both sides of
  decimal point
• e.g. 5.7, 0.1
• Scientific notation
• 23.5E2
• Strings
• sequence of characters within double quotes

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Data Types

• Two groups Net Type and Register Type
• Net Type
• Physical connection between structural elements
• Value determined from value of its drivers
• Value assigned by a continuous assignment or a
  gate output
• No driver connected implies net defaults to a
  value of z
• Register Type
• represents abstract data storage element
• Assigned values only within an always statement
  or an initial statement
• Value saved from one assignment to the next
• register type has default value of x

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Net Types

• wire supported by Quartus
• tri supported by Quartus
• wor
• trior
• wand
• triand
• trireg
• tri1
• tri0
• supply0
• supply1

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Net Declaration Syntax

• net_kind msblsb net1,net2, .net N
• net_kind is one of the types of nets supported
  (Quartus implies only wire and tri nets)
• msb and lsb are constant expressions that specify
  the range of the net
• If no range is specified, range defaults to one
  bit
• Examples
• wire clk, a, b // Three one-bit wire nets
• wire 30 A, B // Two four-bit wire nets
• wire range-10 busA //a parameterized net
  declaration
• tri nets have same declaration form as wire nets
• Use tri nets when multiple drivers drive a net

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Register Types

• Five kinds in Verilog
• reg supported by Quartus
• integer
• time
• real
• realtime
• reg is most commonly used
• Syntax
• reg msblsb reg1, reg2, reg N
• Examples
• reg 30 A, B //declares two 4-bit
  registers
• reg Cnt //declares a one-bit
  register

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Parameters

• Constant used to specify elements which can vary
  from use to use
• Example
• parameter Word 32

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Expressions

• Consists of operators and operands
• Used wherever a value is expected

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Operands

• Constant
• Parameter
• Net
• Register
• Bit-Select
• Part-Select
• Memory element
• Function call

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Bit-select

• Extracts a particular bit from a vector
• Format
• net_or_reg_vector bit_select_expression
• Example
• addreg31 //references bit 31 of the
  register addreg

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Part-select

• Extracts a contiguous sequence of bits of a
  vector
• Format
• net_or_reg_vector msb_const_exprlsb_const_expr
  
• range expressions must be constant expressions
• Example
• addreg3126 //references most significant 6
  bits of register addreg

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Operators

• Verilog uses following operator categories
• arithmetic
• Relational
• Equality
• Logical
• Bitwise
• Reduction
• Shift
• Conditional
• Concatenation and replication

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Table of Operators
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Table of Operators (cont)
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Table of Operators (cont)
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Table of Operators (cont)
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Continuous Assignment

• Used to model data flow behavior
• Assigns a value to a net (cannot be used to
  assign a value to a register)
• Example (full adder)

//fulladder.v //Full Adder Module using minterm
equations module fulladder(a,b,cin, sum,
cout) input a, b, cin output sum,
cout assign sum !a !b cin !a b
!cin a !b !cin a b cin assign
cout !a b cin a !b cin a
b !cin a b cin endmodule
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Continuous Assignment (cont)

• Continuous assignment executes whenever an event
  (change of value) occurs for an operand used in
  the right-hand side of the expression
• Target in a continuous assignment statement
• scalar net
• vector net
• constant bit-select of a vector
• constant part-select of a vector
• concatenation of any of the above
• Can appear as part of a net declaration
• Example
• wire Clear
• assign Clear b1
• is equivalent to
• wire Clear b1

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Procedural Constructs (Behavioral Modeling)

• Assignment to registers always statement
• executes repeatedly
• Always Statement Syntax
• always timing_control procedural_statement
• timing_control may be a delay control, or an
  event control
• procedural_statement is one of the following
• procedural_assignment (blocking or non-blocking)
• procedural_continuous_assignment
• conditional_statement
• case_statement
• loop_statement
• wait_statement
• disable_statement
• event_trigger
• sequential_block (begin end)
• parallel_block
• task_enable (user or system)

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always statement

• Examples
• always
• _at_ (negedge Clk)
• begin
• .
• .
• .
• end
• The timing control is on the negative edge of the
  clock
• The procedural code is enclosed between begin and
  end

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Event Control

• Edge-triggered or level-sensitive
• Edge-triggered
• _at_ event procedural_statement
• e.g.
• _at_ (posedge Clock)
• current_state next_state
• _at_ (posedge Clear or negedge Reset)
• Q 0
• Level-sensitive Edge Control
• delay procedural statement until an event becomes
  true
• wait (condition) procedural_statement
• Example
• wait (DataReady)
• Data Bus

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Latch Example

• D latch
• The output, Q, follows the input, D, as long as
  control is enabled
• Verilog Example

D Q C !Q
//D_latch.v //Verilog file to describe a D
latch module D_latch (Q, D, control) output
Q input D, control reg Q always _at_ (control
or D) if (control) Q D endmodule
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Flip-flop Example
Set D Q Clk !Q Rst

• D flip-flop
• Q follows D on positive edge transition of clock
• May have asynchronous set and clear (reset)
  inputs
• Verilog Example

//D_FF.v //D flip-flop example with set and reset
asynchronous inputs module D_FF (Q, D, CLK, SET,
RST) output Q input D, CLK, SET, RST reg
Q always _at_ (posedge CLK or negedge RST or
negedge SET) if (RST) Q 1'b0 else if
(SET) Q 1'b1 else Q
D endmodule
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Basic Design Methodology

• Modern Designs are Complex
• Thousands to millions of gates
• First prototypes must either work or require only
  a few corrections
• Debugging designs much easier at Verilog stage
  than at hardware stage
• Good Design Teams Enforce a Disciplined Approach
• Process to follow
• Rules about design approach
• Constraints
• Modular approaches
• Hierarchical structures

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Design Flow for Small Modules
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Design Specification

• Deals with behavior and interface of each module
  in the design
• Covers multiple levels
• At Module Level, Specification Should Include
• Description of top-level behavior of the module
• Description of all inputs and outputs
• Description of I/O timing and constraints
• Performance requirements and constraints
• May include behavioral prototyping
• Develop software simulation of total design and
  significant modules
• Use your favorite language (C, C, Java, Basic,
  etc.)
• Use specialized languages

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Specification ExampleFour-bit slice, ripple
carry adder module

• Inputs
• Two 4-bit vectors(A30 and B30)
• A 1-bit carry-in (used to concatenate bit slices)
• Outputs
• A 4-bit sum, S30
• A 1-bit carry-out (used to concatenate bit slices
  and to indicate overflow)
• Functional Behavior
• Forms S ABcarry-in
• Generates carry-out as required
• Timing
• Operates asynchronously
• Generates stable Sum and Carry-out within 10
  gate-delays of inputs becoming stable
• Other Considerations
• None (for now)

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Design Structure

• Obtain/Specify Sub-modules Required
• Continue this process until the lowest level
  module is defined or embedded primitives can be
  used
• Determine the control strategy (if any)
• Clearly separate data path from control
• Determine the register transfer level of the
  design
• Module I/O
• Identify, name, and determine the function of
  each module input/output signal
• Registers and register outputs
• Identify each register and name register outputs
• Determine register clocking
• Combinatorial Logic Blocks and their functions
• Identify blocks of combinatorial logic, their
  functions, and name their signals

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Structure ExampleFour-bit slice, ripple carry
adder module

• Sub-module Full-adder
• I/O
• Inputs
• One-bit quantities a, b, and carry-in
• Outputs
• One-bit quantities sum and carry-out
• Functional behavior
• Forms s a b carry-in
• Generates carry-out if necessary
• Timing
• Operates asynchronously
• Generates stable Sum and Carry-out within 10
  gate-delays of inputs becoming stable
• Other Considerations
• None (for now)

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Structure Example (cont)Four-bit slice, ripple
carry adder module

• Determine the control strategy (if any)
• Asynchronous
• Determine the register transfer level of the
  design
• Module I/O
• FA0full adder for bit 0
• Inputs A0, B0, carry-in
• Outputs S0, c0
• FA1 full adder for bit 1
• Inputs A1, B1, carry-in
• Outputs S1, c1
• FA2 full adder for bit 2
• Inputs A2, B2, carry-in
• Outputs S2, c2
• FA3 full adder for bit 3
• Inputs A3, B3, carry-in
• Outputs S1, carry-out
• Registers and register outputs-- None
• Combinatorial Logic Blocks and their functions
  (see above)

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Design Entry

• Create Verilog description for each sub-module
• Create Verilog description for the module by
  connecting the sub-modules and (possibly
  additional logic)

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Design Entry Example Four-bit slice, ripple
carry adder module

• Sub-module full-adder

//fulladder.v module fulladder (a, b, cin, sum,
cout) input a, b, cin output sum,
cout assign cout, sum a b cin
//behavioral assignment endmodule
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Design Entry Example (Cont) Four-bit slice,
ripple carry adder module

• //add_4_rc.v
• //Four-bit ripple carry adder example
• //Uses fulladder.v module
• module add_4_rc(A, B, cin, SUM, cout)
• input 30 A,B
• input cin
• output 30 SUM
• output cout
• wire c0,c1,c2
• fulladder FA3(A3, B3, c2, SUM3, cout)
• fulladder FA2(A2, B2, c1, SUM2, c2)
• fulladder FA1(A1, B1, c0, SUM1, c1)
• fulladder FA0(A0, B0, cin, SUM0, c0)
• endmodule