Static Statistical Timing Analysis for Latchbased Pipeline Designs

1
Static Statistical Timing Analysis for
Latch-based Pipeline Designs

• Mango C.-T. Chao, Li-C Wang, Kwang-Ting Cheng,
• Department of Electrical Computer Engineering
• UC Santa Barbara, CA

Sandip Kundu Intel Corporation Austin, Texas
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Outline

• Motivation Problem Formulation
• Our Statistical Timing Analyzer, STAP
• Experimental Results
• Conclusions

3
Motivation

• Process variations exercise more and more
  influences over timing characteristics
• gate length fluctuation, subwavelength
  lithography, noise, power..
• Case-delay timing model is no longer enough
• Statistical timing analysis is proposed to cope
  with the variation effects
• Using level-sensitive latches is a popular
  technique for high-performance designs
• All previous statistical timing analyzers are for
  edge-triggered flip-flop designs

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Timing Constraints for Level-sensitive Latches
TC
TP
departure time
arrival time
clock signal
latch i to latch j
latch j to latch k
latch k to latch m
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Timing Constraints for Level-sensitive Latches
TC
TP
departure time
arrival time
clock signal
latch i to latch j
latch j to latch k
latch k to latch m
aiearliest signal arrival time on latch i
SMO model, early-mode analysis
diearliest signal departure time on latch i
dj max (ai , Tc TPi)
?jishortest path delay from j to i
ai min (dj ?ji - EPjPi), for all ij
Hi hold time of latch i
ai Hi
hold time constraint
TC clock period
TPi width of the active interval of latch phase
Pi
EPjPi forward phase shift form phase Pi to phase
Pj
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Objective of STA for Latch-based Pipeline Design
Stage 1
Stage 2
Stage 3
Stage 4
PIs
POs
latches
latches
latches

• Given
• All random variables of cell delay and wire delay
• Desired clock frequency and clock phase
• Setup time and hold time for each latch
• Objective
• Report CCP (Circuit Critical Probability)

Prob Capturing wrong data at any PO
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Critical Probability of Latch in Pipeline Design
Stage 1
Stage 2
Stage 3
Stage 4
i
PIs
POs
latches
latches
latches
ICEi Integrated Critical Event of latch i
latch i stores a wrong data
CECSi U CEPSi
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Critical Probability of Latch in Pipeline Design
Stage 1
Stage 2
Stage 3
Stage 4
i
j
PIs
POs
latches
latches
latches
CECSi Critical Event of i associated with
Current Stage
latch i stores a wrong data due to a long
delay in the current stage
Prob CECSi Prob Ai Tc TPi Si
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Critical Probability of Latch in Pipeline Design
Stage 1
Stage 2
Stage 3
Stage 4
i
j
PIs
POs
k
latches
latches
latches
CEPSi Critical Event of i associated with
Previous Stage
latch j in the previous stage stores a wrong
data and propagate to latch i
Prob CEPSi Prob ICEj
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Outline

• Introduction Problem Formulation
• Our Statistical Timing Analyzer, STAP
• Experimental Results
• Conclusions

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Tasks in STA for Latch-based Pipeline Designs
Stage 1
Stage 2
Stage 3
Stage 4
i
j
PIs
POs
k
latches
latches
latches

• Calculate statistical worst-case delay (ex. Ai,
  ai)
• , Max, Min operations over random
  variables
• Propagate critical probabilities from stage to
  stage
• U (OR) operation over different critical events
  of different pipeline stages
• Handle correlation of delay random variables
  within a stage or across stages

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Statistical Worst-case Delay Computation

• The greatest of a finite set of random
  variable, C.E. Clark, Operation Research, 1961
• Can handle correlation between random variables
• C. Visweswariah, et. al., DAC 2004
• H. Chang, et. al., ICCAD 2003

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Propagate Worst-case Delays Operation of
Random Variables

• Given two normal random variables, X(?x,?x2),
  Y(?y,?y2), and their correlation coefficient ?xy
• Output delay Z(?z,?z2) of two cascaded variables
  X and Y, denoted by ZXY

Y
X
Z
(1)
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Propagate Worst-case DelayMax Operation of
Random Variables

• Output delay Z(?z,?z2) of the maximum operation
  of two random variables, denoted by ZmaxX,Y

X(?x,?x2)
Z(?z,?z2)
Y(?y,?y2)
(2)
where,
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Propagate Worst-case DelayMin Operation of
Random Variables

• Output delay Z(?z,?z2) of the minimum operation
  of two random variables, denoted by ZminX,Y

X(?x,?x2)
Z(?z,?z2)
Y(?y,?y2)
(3)
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Propagate Critical Probability Or Operation
of Random Variables

• After propagating worst-case delay, we compute
  CPCS(i) by setup time constraint
• Represent critical probability by a normal
  distribution n and a constant c
• To compute CPPS(i) and ICP(i), we
• have to do OR operation on two
• critical probabilities (n1, c1) and (n2, c2)
• When c1 c2 c,
• When c1 ? c2,

Aj Tc Tpi - Si
Prob n1 gt c ? n2 gt c 1 - Prob Max(n1, n2)
c
Prob Max(n1, n2) gt c
Probn1 gt c1 ? n2 gt c2 Prob Max(n1, n2 c1
c2) gt c1
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Necessity of Or Operation
Stage 1
Stage 2
Stage 3
Stage 4
i
j
PIs
POs
k
latches
latches
latches

• Dependence of delays across stages
• Cannot represent the critical probability by a
  constant and do the OR operation by
  multiplications and subtractions
• Ex. Prob CECPi 0.1, Prob CECPj 0.2

Prob CECPi U CECPj ? 1- (1-0.1)(1-0.2)
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Correlation between Random Variables

• Sources of correlation
• Spatial correlation and reconvergent fanout
• Spatial correlations are pre-characterized in
  timing model before applying STA
• Correlation due to reconvergent fanout cannot be
  pre-characterized before applying STA
• Covariance matrix has to be built dynamically
  during the STA process

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Correlation List

• Record non-zero correlation coefficient with
  other RVs (random variable)
• After every or Max operation
• The output RV inherits the correlation list from
  its input RVs
• Update the correlation coefficient with Equation
  (1) or (2)
• Two reduction rules for correlation list
• Remove correlation coefficient smaller than a
  threshold
• Remove correlation coefficient of a RV whose
  outputs are all traversed

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Correlation List
rv1
rv2
rv3
rv1 _ ?12 ?13
rv2 ?21 _ ?23
rv3 ?31 ?32 _
rv1
rv4
rv2
rv3
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Outline

• Introduction Problem Formulation
• Our Statistical Timing Analyzer
• Experimental Results
• Conclusions

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Experimental Results

• Pipeline design benchmarks
• Cut ISCAS benchmarks into 4 pipeline stages by
  balancing its topological depth
• Monte-Carlo statistical timing analyzer (MC_STA)
• 10000 sample instances

CCP (Circuit critical probability, ) comparison
between MC_STA and STAP on c6288
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Experimental ResultsAccuracy and Runtime
Comparison
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Experimental ResultsCorrelation Consideration
STA_No_Cor STA without considering any
correlation
STA_Stage_Indep STA without considering
correlation
among stages
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Experimental ResultsCorrelation List Reduction
Accuracy remains the same with applying reduction
rules
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Conclusion

• Propose a static statistical timing analyzer for
  latch-based pipeline designs
• Propagate statistical worst-case delays as well
  as critical probabilities through pipeline stages
• Demonstrate the impact of correlation caused by
  reconvergent fanouts for latch-based designs
• Propose an efficient dynamic method for
  maintaining correlation list
• Show the accuracy of STAP by comparing with a
  Monte-Carlo timing analyzer

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• Thank You !!