VHDL Data types, Generics, Blocks

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VHDL Data types, Generics, Blocks

• Session - V

Prof. B V Uma, RVCE, Bangalore
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Contents

• Wait Statement
• Assert Statement
• VHDL data types
• Generics

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Exit statement

• Syntax
• exit loop_labelwhen condition
• Example for Exit statement
• Sum1
• L3 Loop
• Sumsum10
• If sum gt100 then
• Exit L3
• End if
• End loop L3

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Wait Statement

• This statement may only be used in processes
  without a sensitivity_list.
• Syntax wait on signal_names wait until
  conditionwait for time_expression

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D flip flop model using wait statement

• library ieee
• use ieee.std_logic_1164.all
• entity dff is
• Port (reset, d in std_logic
• clock in std_logic
• q out std_logic)
• end dff

Cont
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• architecture behv of dff is
• begin
• process
• begin
• --asynchronous reset input
• if (reset0) then qlt0
• -- clock rising edge
• elsif (clock'1' and clock'event) then
• qlt d
• end if
• wait on reset, clock
• end process
• end behv

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wait until condition

• Process
• Begin
• Wait until clock1 and clockevent If
  (reset0) then
• Qlt0
• Else qltd
• End if
• End process

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wait for time_expression

• Process
• Begin
• Alt0 Wait for 5ns
• Alt1 Wait for 5ns
• End process
• wait on int for 5ns
• wait on ale until (ale1) for 5ns

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Assert Statement

• Syntax assert condition report string_expr
• severity failureerrorwarningnote
• Example To report error when SetReset0 in D
  or JK Flip flop
• Assert (Set1 or Reset 1)
• Report Set and Reset both are 0
• Severity ERROR

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Set up time in D flipflop

• Process ( clk)
• Begin
• Assert (Clk 1 and ClkEvent and DSTABLE(3
  ns))
• Report Setup time violation
• Severity ERROR

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• If the condition inside the assert statement is
  false, the statement outputs a user specified
  text string
• severity terminates the program compilation
  depending on severity level.

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Severity Levels

• Note
• Warning
• Error
• Failure

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VHDL data types
Data Types
File
Access
Scalar
Composite
Enumerated
Real
Integer
Physical
Array
Record
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Enumerated Types

• Type Fourval is (X, 0, 1, Z)
• Type Four is (X, 0, 1, Z)
• Type color is (red, yellow, blue, green, orange)
• Type Instruction is (add, sub, lda, ldb, sta,
  stb, outa, xfr)
• Real type example
• Type input level is range -10.0 to 10.0
• Type probability is range 0.0 to 1.0

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Example for enumerated type- Simple
Microprocessor model

• Package instr is
• Type instruction is (add, sub, lda, ldb, sta,
  stb, outa, xfr)
• End instr
• Use work.instr.all
• Entity mp is
• PORT (instr in Instruction
• Addr in Integer
• Data inout integer)
• End mp

Cont
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• Architecture mp of mp is
• Begin
• Process (instr)
• type reg is array(0 to 255) of integer
• variable a,b integer
• variable reg reg

Cont
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• begin
• case instr is
• when lda gt adata
• when ldb gt bdata
• when add gt aab
• when sub gt aa-b
• when sta gt reg(addr) a
• when stb gt reg(addr) b
• when outa gt data a
• when xfr gt ab
• end case
• end process
• end mp

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Physical types

• Syntax
• Type _____ is range _____ to _____
• Units identifier
• (identifierphysical literal)
• end units identifier
• Example
• Type current is range 0 to 10,000,00
• units
• na
• ua 1000na
• ma 1000ua
• a 1000ma
• end units

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Composite Types

• Arrays
• Array types are groups of elements of same type
• Records
• Record allow the grouping of elements of
  different types

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Array Type

• Syntax
• Type username is array (lower_limit to
  upper_limit) of datatype
• Example Single Dimension Array
• Type data-bus is array (0 to 31) of BIT

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Two Dimensional array

• Example
• (1) Type matrix4x3 is array (1 to 4, 1 to 3) of
  integer
• (2) Type data_word is array(7 downto 0) of
  std_logic
• Type ROM is array(0 to 255) of data_word

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Record Type

• Example
• Type optype is (add, sub, mpy, div, cmp)
• Type instruction is
• Record
• Opcode optype
• Src integer
• Dst integer
• End record

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Generics

• Generics are a general mechanism used to pass
  information to an instance entity.
• Generics are a means of communicating non
  hardware and non signal information between
  designs.

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Generic for Structure Design

• Entity test_Gen is
• Generic (nise, fall Time)
• Port(a,b in std_logic c out std_logic)
• End test
• Architecture test_arch of test_Gen is
• Component AND2
• Generic (rise, fall Time)
• Port(a,b in std_logic c out std_logic)
• End component
• Begin
• U1 AND2 Generic Map (10ns, 12ns)
• Port map (ia, ib, oc)
• End test_arch

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Generic for Behavioral Design

• entity nand2 is
• generic (tr Time 6ns
• tf Time 4ns)
• port(i1, i2 in BIT y1 out BIT)
• end nand2
• architecture delay of nand2 is
• Signal tbit
• Begin
• tlt i1 NAND i2
• y1lt t after tr when (t1) else
• t after tf
• end delay

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VHDL code for n-bit counter

• library ieee
• use ieee.std_logic_1164.all
• use ieee.std_logic_unsigned.all
• entity counter is
• Generic (n natural 8)
• Port ( clock in std_logic
• clear in std_logic
• count in std_logic
• Q out std_logic_vector(n-1 downto 0)
• )
• end counter

Cont
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• architecture behv of counter is
• signal Pre_Q std_logic_vector(n-1 downto 0)
• begin
• -- behavior describe the counter
• process (clock, count, clear)
• begin
• if clear '1' then
• Pre_Q lt Pre_Q - Pre_Q
• elsif (clock'1' and clock'event) then
• if count '1' then
• Pre_Q lt Pre_Q 1
• end if
• end if
• end process
• Q lt Pre_Q
• end behv

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VHDL code to implement the functionality of 83
Encoder without Priority

• library ieee
• use ieee.std_logic_1164.all
• entity penc83 is
• Port ( d in std_logic_vector(7 downto 0)
• b out std_logic_vector(2 downto 0))
• end penc83
• architecture Behavioral of penc83 is
• begin

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• process(d)
• begin
• case d is
• when "00000001" gt b lt "000"
• when "00000010" gt b lt "001"
• when "00000100" gt b lt "010"
• when "00001000" gt b lt "011"
• when "00010000" gt b lt "100"
• when "00100000" gt b lt "101"
• when "01000000" gt b lt "110"
• when "10000000" gt b lt "111"
• when othersgtNULL end caseend process
• end Behavioral

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VHDL code to implement the functionality of 24
decoder with active low enable input.

• library ieee
• use ieee.std_logic_1164.all
• entity DEC24 is
• Port ( i in std_logic_vector(1 downto 0)
• e in std_logic
• y out std_logic_vector(3 downto
  0))
• end DEC24
• architecture Behavioral of DEC24 is
• begin
• process(i,e)

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• begin
• if (e1) then ylt0000
• else
• case i is
• when "00"gtylt"0001"
• when "01"gtylt"0010"
• when "10"gtylt"0100"
• when "11"gtylt"1000"
• when othersgtNULL
• end caseend ifend process
• end Behavioral

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THANK YOU