Sebastian Loeda BEng(Hons)

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Sebastian Loeda BEng(Hons)

• The analysis and design of low-oversampling,
  continuous-time ?? converters and the effects of
  analog circuits on loop stability and performance

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Overview
The analysis and design of low-oversampling,
continuous-time ?? converters and the effects of
analog circuits on loop stability and performance

• Background
• Low oversampling, continuous-time ?? converters
• Loop delay effects
• Loop delay compensation by optimization
• Integrator circuit response finite DC gain
• Integrator circuit response high frequency pole
• Conclusion
• Future work

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Introduction

• A/D converter bottleneck to any sensor system
• Particularly true for radar
• ?? conversion achieves high-resolution with
• Oversampling (error averaging),
• Limited by technology and bandwidth (here is low)
  
• Feedback (quantization noise shaping)
• Limited by the order of H(s), and may be unstable!

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Analysis of CT ??

• Challenge due to mix of DT and CT
• Create a DT model of the noise response
• Model the quantization noise transfer function
  (NTF)
• NTF(z) 1/(1H(z))
• Mapping cannot be an approximation!

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Poles and zeros of NTF(z)
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Loop delayNTF(z)
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Loop delay SNR
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Design-by-optimization
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Loop delay t compensationResonator H(s) fixed
poles
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Loop delay t compensationFree poles of H(s)
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Resonator Vs Free poles of H(s)

• Two regimes
• Resonator optimum for low values of t ( 0.2)
• Real poles optimum for moderate values of t
• But lose noise notch
• Unusual!
• What about H(s)?

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Ideal integrator model in H(s)large OSRs
H(s)
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Realistic integrators

• Finite DC gain
• High frequency poles and zeros
• What is the impact of circuits on the loop
  performance and stability for low OSR?

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Illustrative exampleIntegrator model to second
order
(?2 proportion of sampling frequency)
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Effects of finite DC gainNTF(z)
Start 100dB
End 0dB
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Effects of finite DC gain SNR
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Effects of second pole ?2NTF(z)
Start 10fs Hz
End 0.5fs Hz
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Effects of second poles ?2 NTF(z) (altogether)
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Effects of second poles ?2 SNR
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Summary

• First integrator stage is critical
• Wide bandwidth required but
• Must be low noise!
• The later the stage the lesser the effect
• Third a bit more sensitive than expected
• due to feedback in H(s), i.e. zeros of NTF(z)

• Can cope with loop delay
• Use of real poles of H(s)
• DC has a limited effect
• As long as it is kept reasonably high
• But note 3rd unusually sensitive
• ?2 is very important!
• Gets worse with low OSR
• Only one pole considered for illustrative
  purposes!

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Conclusions

• With low OSRs, cannot design a CT ?? without
  taking into consideration the integrator
  circuits response!
• Compensation
• Add zeros in In(s)
• What are the optimal zero positions?
• Mitigate circuit effects by optimising the model
• Expect similar mitigation seen for loop delay

• Advantages of design-by-optimization
• Optimum has zero matrix jacobian, i.e. robust
• Add circuit design criteria as optimization
  constraints (e.g. bound component sizes)
• Caveat
• Depends on how well characterised the technology
  is

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Future work

• Achievements
• Generalised the mapping for
• Any H(s)
• DAC shape and timings
• OSR
• Fast, general and accurate
• Essential for more sophisticated integrator/DAC
  models
• Assess the impact of circuits on CT ?? with a
  z-domain model
• Developed a design-by-optimization technique

• Future aims
• Create integrator models from realistic circuits
• Optimise directly on component values
• Cascaded CT ??
• Practical advantages
• Increase performance out of good integrator
  circuit
• Reduce cost with primitive integrator

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Qs (hopefully) As

• Thank you!