Timing Analysis for Partially Specified Vectors TAPSV

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Timing Analysis for Partially Specified Vectors
(TA-PSV)

• Liang-Chi Chen, Sandeep K. Gupta, Melvin A.
  Breuer
• EE-Systems, University of Southern California

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IntroductionTraditional Timing Calculation

• Static timing analysis (STA) implicitly compute
  min/max timing ranges for space of all input
  transitions
• Timing simulation (TS) compute arrival and
  transition times for a pair of completely
  specified input vectors
• Deficiency when input vectors are partially
  specified, timing ranges will usually be smaller
  than that in STA. TS usually does not compute
  timing ranges
• Contribution a new timing refinement method to
  compute timing ranges for partially specified
  vectors

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IntroductionTiming Analysis for Partially
Specified Vectors

• Motivation to prune ATPG search space
• in test/validation
• Test generation (using PODEM) binary values are
  successively assigned to circuit inputs
• Features
• As values are assigned to circuit lines during
  ATPG, min-max timing ranges are refined
  incrementally to provide better timing
  information
• Consider partially specified input values

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Static Timing AnalysisExample - Find Latest
Output Arrival Time

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TA-PSVDuring Test Generation

• Static timing analysis provides min-max timing
  ranges for all possible transitions at each line
• TA-PSV computes tighter timing ranges when some
  inputs are specified
• For a completely specified vector, TA-PSV becomes
  identical to timing simulation
• Key issue for each gate, identify the worst case
  corners for the terms to be calculated (A, T, or
  Q) for all cases where inputs are partially
  specified

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TA-PSVRefinement of Logic Value

Worst Case Corners for Justification
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TA-PSV Problem and Proposed Solution

• Problem possible input combination 9 logic
  values at each of n lines ? 9n combinations
• Proposed Solution

Value reduction
Formula generalization
2 inputs
9n combinations ? 22 combinations
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Experiment Results TA-PSV

• Total timing range shrink as more inputs are
  specified.

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Experiment Results Test Generation on crosstalk
delay

• Test efficiency of target faults can be
  captured
• Comparing test efficiency of ATPGs with/without
  TA-PSV for similar run time.
• TA-PSV increases test efficiency to acceptable
  (? 80)

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Summary

• TA-PSV enables the computation of tight timing
  windows when input vectors are partially
  specified
• We propose a method to identify the worst case
  corners, demonstrated on an accurate delay model,
  and compute more accurate timing ranges than STA
• TA-PSV can bound timing ranges and hence reduce
  the search space for timing-oriented test
  generation
• TA-PSV can also provide more accurate timing
  ranges during timing validation
• We show how TA-PSV significantly reduces timing
  windows on the ISCAS85 benchmark circuits
• We demonstrate how ATPG efficiency is
  significantly improved by TA-PSV