Machine Instructions

1
Machine Instructions

• ECE-445
• Computer Organization
• Dr. Ron Hayne
• Electrical and Computer Engineering

2
Processor and Memory
MEM
MAR
MDR
Control
PC
R0
R1
IR
...
ALU
Rn-1
Processor
MAR - Memory Address Register MDR - Memory Data
Register
PC - Program Counter IR - Instruction Register
3
Memory Organization

• Dimensions
• n-bit words
• k-bit address
• Operations
• Read, Load, Fetch
• Write, Store

n bits
Address
0
first word
next word
1
...
last word
2k-1
Memory
4
Memory Detail (HW 1)
MEM
MAR
BUS_A
REG2
ADDRESS
MEM_DUMP
DATA_OUT
DATA_IN
Enable_Out
Enable_In
CLK
RAM 4x16
Write
Enable_In1
Enable_Out2
DATA_OUT
DATA_IN1
DATA_OUT2
REG16_2PORT
Read
DATA_IN
DATA_OUT1
DATA_IN2
Enable_Out1
Enable_In2
CLK
CLK
MDR
5
Byte Addressability

• Byte 8 bits
• Word 16 to 64 bits
• Variable length strings
• "end of string" character
• length of string

16 bits
. . .
b15
b14
b0
Sign bit
8 bits
8 bits
ASCIIcharacter
ASCIIcharacter
6
Byte Addressability
Wordaddress
Wordaddress
Byte address
Byte address
0
0
1
2
3
0
3
2
1
0
4
4
5
6
7
4
7
6
5
4
...
...
2k-4
2k-4
2k-3
2k-2
2k-1
2k-4
2k-1
2k-2
2k-3
2k-4
Big-endianassignment
Little-endianassignment
7
Instruction Types

• One-address
• Operation Source/Destination (other implied)
• LOAD A
• Two-address
• Operation Source,Destination
• MOVE A,R1
• Three-address
• Operation Source1,Source2,Destination
• ADD R1,R2,R3

8
One-Address Instructions

• Assembly Language
• LOAD A
• ADD B
• STORE C

• Register Transfer Notation
• AC ? A
• AC ? B AC
• C ? AC

9
Multi-Address Instructions

• Assembly Language
• MOVE A,R1
• ADD B,R1
• MOVE R1,C
• ADD R1,R2,R3

• Register Transfer Notation
• R1 ? A
• R1 ? B R1
• C ? R1
• R3 ? R1 R2

10
Instruction Sequencing

• PC
• Instruction Address
• Fetch
• Increment PC
• IR
• Execute Instruction
• Example
• C ? A B

Contents
Address
i
MOVE A,R1
3-instructionprogramsegment
i1
ADD B,R1
i2
MOVE R1,C
...
A
...
Data forthe program
B
C
11
Adding n Numbers
i
MOVE NUM1,R0
i1
ADD NUM2,R0
i2
ADD NUM3,R0
...
in-1
ADD NUMn,R0
in
MOVE R0,SUM
...
SUM
NUM1
NUM2
...
NUMn
12
Branching
MOVE N,R1
Counter
CLEAR R0
Accumulator
Determine address of "Next" number and add "Next"
number to R0
LOOP
Programloop
DECREMENT R1
BRANCHgt0 LOOP
PC ? PC Offset (CCgt0)
MOVE R0,SUM
...
SUM
N
n
NUM1
...
NUMn
13
Condition Code Flags

• N (negative) Set to 1 if result is negative
• N R15
• Z (zero) Set to 1 if result is zero
• Z not (R15 or R14 or or R0)
• V (overflow) Set to 1 if arithmetic overflow
  occurs
• V (A15 and B15 and not S15) or (not A15 and not
  B15 and S15)
• C (carry) Set to 1 if a carry-out results
• C C16

Note otherwise cleared to 0
14
Additional Instructions

• Assembly Language
• NOT R2
• NEGATE R0
• AND B,R1
• COMPARE R1,R2
• MULTIPLY R1,R2

• Register Transfer Notation
• R2 ? not R2
• R0 ? not R0 1
• R1 ? B and R1
• R2 - R1
• R2 R3 ? R1 x R2

15
Shift Instructions
16
Rotate Instructions
17
Homework 1

• Single-Bus Architecture
• Control for Memory, Registers and ALU
• Implement Single RTN Function
• MEM(3) ? MEM(1) MEM(2)
• Testbench to Verify Memory Contents

18
Single-Bus Architecture

• 16 bit Datapath
• 4 Word Memory
• MAR (2 bits)
• MDR
• 8 Function ALU
• 2 ALU Registers
• Y
• Z

19
Single-Bus Architecture
BUS A
MAR
MEM
MDR
Y
A
B
ALU
R
Z
20
16 Bit Register

• REG16

BUS_A
Y
Enable_Out
Enable_In
REG16
DATA_IN
CLK
DATA_OUT
21
Datapath

• Signals
• MAR_IN
• MAR_OUT
• MDR_IN1
• MDR_OUT1
• Y_OUT
• Z_IN
• Bus Connections
• MDR_IN2 lt BUS_A
• BUS_A lt MDR_OUT2
• Y_IN lt BUS_A
• BUS_A lt Z_OUT

BUS A
MAR
MEM
MDR
1
2
Y
A
B
ALU
R
Z
22
Control Signals

• MAR_En_In
• MAR_En_Out 1
• MDR_En_In1
• MDR_En_In2
• MDR_En_Out1 1
• MDR_En_Out2
• Write
• Read
• Y_En_In
• Y_En_Out 1
• Z_En_In
• Z_En_Out
• Op
• Halt

BUS A
MAR
MEM
MDR
1
2
Y
A
B
ALU
R
Z
23
RTN Sequence

• MEM(3) ? MEM(1) MEM(2)

CNT RTN Control Signals
0 MAR ? 1
1 MDR ? MEM(MAR)MAR ? 2
2 Y ? MDRMDR ? MEM(MAR)
3
4
5
6 Halt ? 1
24
RTN Sequence

• MEM(3) ? MEM(1) MEM(2)

CNT RTN Control Signals
0 MAR ? 1 MAR_En_In
1 MDR ? MEM(MAR)MAR ? 2
2 Y ? MDRMDR ? MEM(MAR)
3
4
5
6 Halt ? 1
25
RTN Sequence

• MEM(3) ? MEM(1) MEM(2)

CNT RTN Control Signals
0 MAR ? 1 MAR_En_In
1 MDR ? MEM(MAR)MAR ? 2 Read, MDR_En_In1MAR_En_In
2 Y ? MDRMDR ? MEM(MAR)
3
4
5
6 Halt ? 1
26
Questions?