The frontend electronics for LHCb calorimeters

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The front-end electronics for LHCb calorimeters
On behalf of the LHCb collaboration

• Overview of the system
• The different sub-detector electronics, focusing
  on the three specific ASICs
• Ecal/Hcal (LAL Orsay)
• PS (LPC Clermont-Ferrand)
• SPD (Barcelona)
• Other points of interest

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The LHCb detector
Ionizing particles
PS/SPD 6000 ch pads fibers
ECAL 6000 ch shashlik (Pb-scint)
HCAL 1500 ch tilecal (Fe-scint)
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Calorimeter trigger electronics scheme
(6000 ch)
(6000 ch)
(1500 ch)
(6000 ch)
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40 MHz Front-End Electronics

• 27 identical crates filled with two types of
  Front-End Boards
• allows to provide Preshower or Ecal/Hcal crates
  at low cost
• Motivation for electronics specificity
• High level0 rate (1 MHz) gt time between
  level0 yes can be 25 ns
• gt
  need full information every 25 ns
• High occupancy and high rate gt need for fast
  shaping
• Use of fast photomultiplier gt fast
  shaping is possible

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ECAL/HCAL electronics
In HCAL/ECAL large number of photoelectrons
(50/GEV, 500-1000/GEV) gt pulse shape smooth and
reproducible gt shaping by delay line clipping
and deadtimeless integrator (no switch) gt
with this design pedestals and digital noise are
small and one can obtain a good dynamic range
in a 12-bit/40-MHz ADC followed by a pedestal
subtractor
Simulation plots with short input pulse
INTEGRATOR INPUT SIGNAL
ADC INPUT SIGNAL
T050ns
T0
T025ns
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Ecal/Hcal ASIC schematics
Board implementation
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Ecal/Hcal ASIC performances
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Ecal/Hcal ASIC layout and FEB prototype
AMS BiCMOS 0.8um (1.9 x 2.1 mm2) (60mW/ch)
16-channel prototype of the Ecal/Hcal front-end
board (1999)
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Preshower and SPD requirements

• Preshower (PS) and Scintillator
• Pad Detector (SPD) provide
• PID for L0 electron trigger
• photon/MIP separation by SPD
• electron/pion separation by PS

Various 1-MIP signals Wiggles gt 70 ns parasitic
pickup

• Because of the small number of photoelectrons
  (about 20-30 per MIP), PS SPD have a
  fluctuating pulseshape.
• However, a 25 ns integration contains most of
  the charge (85) as seen on typical 5-MIP signals

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PS ASIC block diagram

• The Preshower requirements are twofold
• for the level 0 trigger, perform the
  identification of electrons and photons while
  rejecting the charged pions. The corresponding
  threshold is about 5MIPs.
• measure the part of energy lost in the PS to
  correct the global calorimeter information.
• gt the useful measurements cover the 1MIP to
  100MIPs range

• Choice of a multiplexed 40MHz real time
  integrator driving a 10-bit ADC.
• LSB value fixed at 1/10 of a MIP, to obtain a
  sufficient precision on the MIP and properly
  cover the required dynamic range.
• The 5MIP threshold will be applied digitally
  beyond the ADC. The precision obtained by a 25ns
  integration on a 5MIP signal is sufficient for
  the trigger system.

On the front-end board

• The ASIC has to perform a clean integration
  every 25ns. Its critical parts are thus fully
  differential.
• It actually consists in two parallel paths each
  running at 20MHz, then multiplexed at the output.

One among 8 channel of the ASIC.
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PS ASIC main building blocks

• Gain-2 stage of the
• output multiplexor
• with parallel compensation.
• Advantages of this scheme
• when compared to
• usual serial compensation
• no loss of dynamic range
• ability two over-compensate
• for taking two successive
• stages into account

First stages of the chip common to differential
mode block and integrator
Output buffer A true push-pull using only NPN
transistors !
AOP with common mode feedback
With a quiescent current of 16ma, its able to
drive a 50ohm cable with a rise time of 3.5ns
with less than 0.5 of non linearity.
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PS ASIC performances
The spreading of the signal over a few clock
periods can be observed here. The corresponding
integrated charge per clock period appears
clearly at the output of the multiplexor. The
linearity remains within a 1 window over the
whole dynamic range.
The plot of the pedestal distribution at the chip
output presents a double peak which is due to the
two independent paths per channel. These offsets
will be subtracted further in the chain. The
noise level appears well below one ADC count.
This plot displays a MIP measured in real
conditions at the extremity of a 15-meter cable.
The peak amplitude is about 10 ADC counts.
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PS ASIC layout and VFE prototype
Prototype of the 8-channel ASIC AMS 0.8u BiCMOS
(2.60 x 4.40 mm2) (100mW/ch)
Prototype of the 64-channel Very Front-End Board
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SPD ASIC block diagram

• The main requirement for the SPD is to perform
  the selection between photons and charged
  particles.
• As seen before, the corresponding threshold is
  necessarily very low (0.5MIP). Thus the potential
  reminder of the signal measured 25ns earlier
  (17) forces us to subtract the same fixed part
  of the preceding charge sample (17).

Like the Preshower ASIC and for the same reasons,
this chip is mostly differential. Its major
difference is that its output is merely digital
(one bit per channel).
One among 8 channel
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SPD ASIC main building blocks
Subtractor
Integrator
Track Hold
Latched comparator
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SPD ASIC current results
Linearity

• General results of the analog part (4-channel
  prototype)
• Offset (Output Zero Error) ltOZEgt 38.6 mV
  ?io 70 mV r.m.s.
• Gain ltVo/Vigt 16.51 (typical pulse) ?io
  0.091 r.m.s. (0,55)
• Treset 5.5 ns (for 1 V output)
• Noise is about 1 mV r.m.s
• Output range is gt?1V for an arbitrary input
  signal.
• Linearity error is lt 0.5 full scale.

Threshold crossing
Threshold precision
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SPD ASIC layout and test board
4-channel prototype test board
Prototype of the 4-channel ASIC AMS 0.8u BiCMOS
(2.64 x 3.12 mm2) (100mW/ch)
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Standard calorimeter backplane
Top part for power supplies, TTC and ECS.
Bottom part for trigger and readout
interconnections.
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Conclusion and other highlights

• The requirements for the electronics of the four
  sub-detectors constituting the LHCb calorimeter
  have led us to design three different and
  specific front-end sub-systems.
• Clermont-Ferrand (LPC) is in charge of the
  electronics for the Preshower, Barcelona of the
  SPD and LAL ORSAY of the Ecal/Hcal.
• Those were however designed to share standard
  elements everywhere possible.
• Three different ASICs have been designed. They
  are all based upon the AMS 0.8u BiCMOS
  technology. Two of them already passed the
  production readiness review.
• The first level trigger requirements led us to
  implement dense interconnections within and
  between the 27 electronics crates.
• There will be about 1000 cables carrying a total
  of 1200Gbit/s.
• Each crate backplane will transfer about
  200Gbit/s.
• The non negligible radiation level led us to
  realize a SEU and SEL hardened design.
• The Preshower and ECAL/HCAL ASICs have
  successfully undergone radiation tests in a
  proton beam (50kRads) and in an ion beam looking
  for the SELs.
• All the other sensitive components are currently
  undergoing the same kind of tests.
• The design of all the boards had itself to take
  this problem into account.