Introduction to Computing Systems and Programming

1
Introduction to Computing Systems and Programming

• Digital Logic Structures

2
Logical Operations

• 0, 1 in a binary value can represent logical
  TRUE 1, or FALSE 0.
• We can perform logical operations on binary bits
  or a set of binary bits, also known as Boolean
  algebra.
• The basic operations are AND, OR, NOT

3
Basic Logic Operations

• Truth Tables of Basic Operations
• Equivalent Notations
• Not A A A
• A and B A.B A?B A intersection B
• A or B AB A?B A union B

OR OR OR
A B AB
0 0 0
0 1 1
1 0 1
1 1 1
AND AND AND
A B A.B
0 0 0
0 1 0
1 0 0
1 1 1
NOT NOT
A A'
0 1
1 0
4
More Logic Operations

• XOR and XNOR

XOR XOR XOR
A B A?B
0 0 0
0 1 1
1 0 1
1 1 0
XNOR XNOR XNOR
A B (A?B)
0 0 1
0 1 0
1 0 0
1 1 1
5
Logical Operations Example

• AND
• useful for clearing bits
• AND with zero 0
• AND with one no change
• OR
• useful for setting bits
• OR with zero no change
• OR with one 1
• NOT
• unary operation -- one argument
• flips every bit

11000101 AND 00001111 00000101
11000101 OR 00001111 11001111
NOT 11000101 00111010
6
Simple Switch Circuit

• Switch open
• No current through circuit
• Light is off
• Vout is 2.9V
• Switch closed
• Short circuit across switch
• Current flows
• Light is on
• Vout is 0V

Switch-based circuits can easily represent two
states on/off, open/closed, voltage/no voltage.
7
Transistor

• Microprocessors contain millions of transistors
• Intel Pentium II 7 million
• Intel Pentium III 28 million
• Intel Pentium 4 54 million
• Logically, each transistor acts as a switch

8
N-type MOS Transistor

• MOS Metal Oxide Semiconductor
• two types N-type and P-type
• N-type
• when Gate has positive voltage,short circuit
  between 1 and 2(switch closed)
• when Gate has zero voltage,open circuit between
  1 and 2(switch open)

Gate 1
Gate 0
Terminal 2 must be connected to GND (0V).
9
P-type MOS Transistor

• P-type is complementary to N-type
• when Gate has positive voltage,open circuit
  between 1 and 2(switch open)
• when Gate has zero voltage,short circuit between
  1 and 2(switch closed)

Gate 1
Gate 0
Terminal 1 must be connected to 2.9V.
10
CMOS Circuit

• Complementary MOS
• Uses both N-type and P-type MOS transistors
• P-type
• Attached to voltage
• Pulls output voltage UP when input is zero
• N-type
• Attached to GND
• Pulls output voltage DOWN when input is one
• For all inputs, make sure that output is either
  connected to GND or to , but not both!

11
Inverter (NOT Gate)
Truth table
In Out
0 V 2.9 V
2.9 V 0 V
In Out
0 1
1 0
12
NOR Gate
2.9 v
P
A
P
B
C
A B C
0 0 1
0 1 0
1 0 0
1 1 0
N
N
0 v
0 v
13
NOR Gate Operation
2.9 v
2.9 v
2.9 v
2.9 v
2.9 v
0 v
P
P
P
0 v
2.9 v
P
0 v
P
P
2.9 v
0 v
0 v
N
N
N
N
N
N
0 v
0 v
0 v
0 v
0 v
0 v
14
OR Gate
A B C
0 0 0
0 1 1
1 0 1
1 1 1
Add inverter to NOR.
15
NAND Gate (AND-NOT)
A B C
0 0 1
0 1 1
1 0 1
1 1 0
16
AND Gate
A B C
0 0 0
0 1 0
1 0 0
1 1 1
Add inverter to NAND.
17
Basic Logic Gates
18
More Inputs

• AND/OR can take any number of inputs.
• AND 1 if all inputs are 1.
• OR 1 if any input is 1.
• Similar for NAND/NOR.
• Can implement with multiple two-input gates,or
  with single CMOS circuit.

19
Logical Completeness

• Can implement ANY truth table with AND, OR, NOT.

A B C D
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 0
1. AND combinations that yield a "1" in the
truth table.
2. OR the resultsof the AND gates.
20
Practice

• Implement the following truth table.

A B C
0 0 0
0 1 1
1 0 1
1 1 0
A B C
0 0 1
0 1 0
1 0 0
1 1 1
21
Summary

• MOS transistors are used as switches to
  implementlogic functions.
• N-type connect to GND, turn on (with 1) to pull
  down to 0
• P-type connect to 2.9V, turn on (with 0) to
  pull up to 1
• Basic gates NOT, NOR, NAND
• Logic functions are usually expressed with AND,
  OR, and NOT
• Properties of logic gates
• Completeness
• can implement any truth table with AND, OR, NOT
• DeMorgan's Law
• convert AND to OR by inverting inputs and output

22
Logic Structures

• We've already seen how to implement truth
  tablesusing AND, OR, and NOT -- an example of
  combinational logic.
• Combinational Logic Circuit
• output depends only on the current inputs
• stateless
• Sequential Logic Circuit
• output depends on the sequence of inputs (past
  and present)
• stores information (state) from past inputs

23
Decoder

• n inputs, 2n outputs
• exactly one output is 1 for each possible input
  pattern

1, iff A,B is 00
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Multiplexer

• n-bit selector and 2n inputs, one output
• output equals one of the inputs, depending on
  selector

4-to-1 MUX
25
Half Adder

• Half Adder
• 2 inputs
• 2 outputs sum and carry

26
Full Adder

• Add two bits and carry-in,produce one-bit sum
  and carry-out.

A B Cin S Cout
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
27
Four-bit Adder
28
Combinational vs. Sequential

• Combinational Circuit
• always gives the same output for a given set of
  inputs
• ex adder always generates sum and
  carry,regardless of previous inputs
• Sequential Circuit
• stores information
• output depends on stored information (state) plus
  input
• so a given input might produce different
  outputs,depending on the stored information
• example ticket counter
• advances when you push the button
• output depends on previous state
• useful for building memory elements and state
  machines

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R-S Latch
1
1
0
1
1
0
1
0
1
1
0
0
1
1

• If both R and S are one, out could be either zero
  or one.
• quiescent state -- holds its previous value
• note if a is 1, b is 0, and vice versa

30
Clearing the R-S latch

• Suppose we start with output 1, then change R
  to zero.

1
0
1
1
Output changes to zero.
1
0
1
1
0
1
0
1
0
0
1
0
31
Setting the R-S Latch

• Suppose we start with output 0, then change S
  to zero.

1
1
0
0
Output changes to one.
1
1
0
0
1
1
0
1
32
R-S Latch

• R S 1
• hold current value in latch
• S 0, R1
• set value to 1
• R 0, S 1
• set value to 0
• R S 0
• both outputs equal one
• final state determined by electrical properties
  of gates
• Dont do it!

33
Gated D-Latch

• Two inputs D (data) and WE (write enable)
• when WE 1, latch is set to value of D
• S NOT(D), R D
• when WE 0, latch holds previous value
• S R 1

34
Register

• A register stores a multi-bit value.
• We use a collection of D-latches, all controlled
  by a common WE.
• When WE1, n-bit value D is written to register.

35
Memory

• Now that we know how to store bits, we can build
  a memory a logical k m array of stored bits.

Address Space number of locations(usually a
power of 2)
k 2n locations
Addressability number of bits per
location(e.g., byte-addressable)
m bits
36
Address Space

• n bits allow the addressing of 2n memory
  locations.
• Example 24 bits can address 224 16,777,216
  locations
• (i.e. 16M locations).
• If each location holds 1 byte then the memory is
  16MB.
• If each location holds one word (32 bits 4
  bytes) then it is 64 MB.

37
Addressability

• Computers are either byte or word addressable -
  i.e. each memory location holds either 8 bits (1
  byte), or a full standard word for that computer
  (typically 32 bits, though now many machines use
  64 bit words).
• Normally, a whole word is written and read at a
  time
• If the computer is word addressable, this is
  simply a single address location.
• If the computer is byte addressable, and uses a
  multi-byte word, then the word address is
  conventionally either that of its most
  significant byte (big endian machines) or of its
  least significant byte (little endian machines).

38
Memory Structure

• Each bit
• is a gated D-latch
• Each location
• consists of w bits (here w 1)
• w 8 if the memory is byte addressable
• Addressing
• n locations means log2n address bits (here 2 bits
  gt 4 locations)
• decoder circuit translates address into 1 of n
  addresses

39
Memory example

• A 22 by 3 bits memory
• two address lines A10
• three data lines D20
• one control line WE

One gated D-latch
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22 x 3 Memory
word WE
word select
input bits
address
write enable
address decoder
output bits
41
Memory details

• This is a not the way actual memory is
  implemented.
• fewer transistors, much more dense, relies on
  electrical properties
• But the logical structure is very similar.
• address decoder
• word select line
• word write enable
• Two basic kinds of RAM (Random Access Memory)
• Static RAM (SRAM)
• fast, maintains data without power
• Dynamic RAM (DRAM)
• slower but denser, bit storage must be
  periodically refreshed

42
Memory building blocks

• Building an 8K byte memory using chips that are
  2K by 4 bits.

• CS chip select
• when set, it enables the addressing, reading and
  writing of that chip.

This is an 8KB byte addressable memory