Memory and Programmable Logic

1
Memory and Programmable Logic

• CIS-3357
• Chapter 6

2
HOMEWORK
6-1, 6-2, 6-8, 6-11, 6-12, 6-13, 6-14, 6-19,
6-20, 6-21, 6-25
Have an even NICER BETTER NICE Day !!
3
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

4
Introduction

• This chapter addresses memory devices and
  programmable logic components
• There are basically 2 types of memory devices
• Random-access memory (RAM)
• Read-only memory (ROM)
• Random-access memory can be read from and written
  to
• Read-only memory can only be read from
• ROM is one form of programmable logic device
• Other devices used are programmable logic arrays
  and programmable array logic

5
Conventional and Array Logic Diagrams
Conventional Symbols
Array Logic Symbols
6
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

7
Random-Access Memory

• A memory unit is a collection of storage and
  associated circuits needed to transfer
  information in and out of devices
• Storage of information occurs in groups of bits
  called WORDS
• Each WORD may represent a number, an instruction,
  one or more alphanumeric characters or any other
  binary coded information
• Typical WORD sizes are 8 bits, 16 bits, and 32
  bits

8
Block Diagram of a Memory Unit
n data input lines
k Address Lines
Memory Unit
Read
2k words
Write
n bits per word
Address range is 2k - 1
n data output lines
K (kilo) means 210
M (mega) means 220
G (giga) means 230
9
1024 X 16 Memory
Memory Address
Decimal
Binary
Memory content
1011010101011100
0000000000
0
0000010101010101
0000000001
1
1000000101011111
0000000010
2
1111110101010101
1111111101
1021
0111110101010011
1111111110
1022
1100110101011100
1111111111
1023
10
Write and Read Operations

• RAM can be read from and written to
• A WRITE signal specifies a transfer-in operation
• A READ signal specifies a transfer-out operation
• When one of these control signal is active, the
  internal memory circuits provide the desired
  function
• Several steps must be accomplished in sequence
  for successful READ and WRITE operations

11
Write Operations

• Transfer the binary address of the desired word
  to the address lines
• Transfer the data bits that must be stored in
  memory to the data input lines
• Activate the WRITE signal input

12
Read Operations

• Transfer the binary address of the desired word
  to the address lines
• Activate the READ signal input

Control Inputs
13
BUS TIMING - WRITE
Write Transaction
T1
T2
T3
T1
Clock
Memory Address
Address Valid
Memory select
Enable
Read/ Write
Write
Data input
Data Valid
Setup Time
14
BUS TIMING - READ
Write Transaction
T1
T2
T3
T1
Clock
Memory Address
Address Valid
Memory select
Enable
Read/ Write
Read
Data input
Data Valid
Setup Time
15
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

16
Memory Decoding

• A memory with m words and n bits per word
  requires mn binary storage cells
• Binary storage cell is the basic building block
  of a memory unit
• The binary storage cell stores 1 bit of
  information
• Normally make with a single transistor if making
  Dynamic RAM chips to get storage density
• Use two transistors if making Static RAM chips to
  get higher performance

17
Memory Cells
Select


Output

Input

Read/Write
Memory Cell Logic Diagram
Select
Input
BC
Output
Read/Write
Equivalent Memory Cell Block Diagram
18
4 x 4 Random Access Memory
Data Inputs
0
Address Inputs
1
2x4 Decoder
2
Memory Select
EN
3
Read/Write
Output Data
19
2 Dimensional 1K x 8 RAM
Y Address Inputs
5x32 Decoder
EN
0
1
2
31
20
X Address Inputs





0










2
5x32 Decoder
1





12
EN




31
Memory Select
Address 01100 10100
X
Y
20
RAM Chip Block Diagram
Input Data
Output Data
Address
Chip Select
Read/Write
1K x 8 RAM Chip Graphic Symbol
21
4K x 8 RAM Block Diagram
Address 11-12
Chip Select Logic
Input Data
Address 1-10
2 x 4 Decoder
Memory Enable
8
10
0
1
2
3

Read/Write
0-1023

1024-2047

2048-3071
8

3072-4095
Output Data
22
1K x 16 RAM Block Diagram
16 Input Data lines
8
8
10

Address
Chip Select

8
8

Read/Write
16 Output Data lines
23
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

24
Error Detection and Correction

• Its not enough to just make a memory
• Complexity of memory may cause occasional errors
  in storing and retrieving the binary information
• We need to also add error detection and
  correction into the hardware to account for bit
  errors that may occur
• Several ways of approaching error detection and
  correction
• Most common error detection technique is Parity
  generation and checking
• Can only detect single bit errors
• Cannot correct any errors
• Need a more sophisticated approach

25
Hamming Code

• Use multiple parity bits instead of just one
• Use k check bits for n data bits
• Total number of bits (nk) ? 2k - 1
• For k 3, n ? 8 - 1 - 3 4
• For k 4, n ? 16 - 1 - 4 11
• Allows for error correcting 1 bit
• Code can be used with words of any length
• To form a new word with (nk) bits
• Number the bit positions from 1 to (nk)
• Those positions numbered as a power of 2 are
  reserved for the parity bits
• Remaining bits are the data bits

26
Hamming Code
8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 Coded Word
P1 P2 1 P4 1 0 0 P8 0 1 0 0

• Calculate each parity bit (even) based on parity
  generation function (XOR) as follows

P1 XOR(3,5,7,9,11) 1 ? 1 ? 0 ? 0 ? 0 0 P2
XOR(3,6,7,10,11) 1 ? 0 ? 0 ? 1 ? 0 0 P4
XOR(5,6,7,12) 1 ? 0 ? 0 ? 0 1 P8
XOR(9,10,11,12) 0 ? 1 ? 0 ? 0 1
27
Hamming Code

• Generate the coded word from the data bits and
  parity bits just calculated as illustrated below

8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 Coded Word
0 0 1 1 1 0 0 1 0 1 0 0

• The coded word is what is stored in memory (or
  transmitted)
• When we want to read this coded word from memory
  we read all twelve bits and perform a parity
  check operation
• The result of the parity check operation
  determines
• If any single bit errors occurred
• The location in the coded word of any single bit
  errors

28
Hamming Code
8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 Coded Word
0 0 1 1 1 0 0 1 0 1 0 0

• Calculate parity check bits over the same
  combination of bits including the corresponding
  parity bit for that combination
• A result C C8C4C2C1 0000 indicates no error
  has occurred

C1 XOR(1,3,5,7,9,11) 0 ? 1 ? 1 ? 0 ? 0 ? 0
0 C2 XOR(2,3,6,7,10,11) 0 ? 1 ? 0 ? 0 ? 1 ? 0
0 C4 XOR(4,5,6,7,12) 1 ? 1 ? 0 ? 0 ? 0
0 C8 XOR(8,9,10,11,12) 1 ? 0 ? 1 ? 0 ? 0 0
29
Hamming Code

• A result C C8C4C2C1? 0000 indicates an error
  has occurred and the 4-bit binary number formed
  by the check bits gives the position of the
  erroneous bit.

8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 0 0 1
1 1 0 0 1 0 1 0 0 No error
1 0 1 1 1 0 0 1 0 1 0
0 Error in bit 1 0 0 1 1 0 0 0
1 0 1 0 0 Error in bit 5
C1
C2
C4
C8
Error in bit 1
Error in bit 5
30
Hamming Code
8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 0 0 1
1 1 0 0 1 0 1 0 0 No error
1 0 1 1 1 0 0 1 0 1 0
0 Error in bit 1 0 0 1 1 0 0 0
1 0 1 0 0 Error in bit 5
C1 XOR(1,3,5,7,9,11) 0 ? 1 ? 1 ? 0 ? 0 ? 0
0 C2 XOR(2,3,6,7,10,11) 0 ? 1 ? 0 ? 0 ? 1 ? 0
0 C4 XOR(4,5,6,7,12) 1 ? 1 ? 0 ? 0 ? 0
0 C8 XOR(8,9,10,11,12) 1 ? 0 ? 1 ? 0 ? 0 0
31
Hamming Code

• We still have a problem detecting 2-bit errors
• If a two bit error occurs, our correction scheme
  will correct a wrong bit
• The solution is to add another parity bit for the
  whole coded word
• P13 XOR(1-nk)
• This allows for correction of 1-bit errors and
  detection of two bit errors

8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 13 Coded Word
0 0 1 1 1 0 0 1 0 1 0 0
P13
32
Hamming Code
8-bit example 11000100 Bit Position 1 2
3 4 5 6 7 8 9 10 11 12 13 Coded Word
0 0 1 1 1 0 0 1 0 1 0 0
P13

• The following for cases can occur
• C C8C4C2C1as before
• P XOR(1-13) checks parity of all stored bits

C 0
P 0
No error occurred
C ? 0
A single error occurred which can be corrected
P 1
A double error occurred which is detected but not
corrected
P 0
C ? 0
C 0
P 1
An error occurred in the P13 bit
33
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

34
Read Only Memory

• Essentially a memory device in which permanent
  binary information is stored
• Binary information is specified by the system
  designer
• Used extensively where binary information does
  not change after initially specified
• Address ROM the same as RAM is addressed
• Do not have input data lines or write circuitry
  to consider

35
ROM Truth Table (Partial)
Inputs
Outputs
I4
A7
A6
A5
A4
I3
I2
I1
I0
A3
A2
A1
A0
0
0
0
0
0
0
1
0
1
0
1
0
0
0
0
0
1
0
1
0
1
1
0
0
1
0
0
0
0
0
1
0
1
0
1
0
1
1
1
1
1
1
0
0
0
1
0
1
0
1
0
0
1
1
1
1
0
0
1
0
1
0
1
0
0
1
1
1
0
1
1
0
1
0
0
0
0
0
1
1
1
1
1
0
1
0
1
1
0
1
1
36
Programmed 32 x 8 ROM
I0
0
x
x
x
1
x
x
x
x
I1
2
x
x
x
x
x
5x32 Decoder
I2
x
x
x
28
I3
x
x
x
29
I4
30
x
x
31
x
x
x
x
x
A0
A1
A2
A3
A4
A5
A6
A7
37
Read Only Memory

• So far we have only discussed the traditional ROM
• Manufacturer generates a ROM from a truth table
  for you
• This procedure is costly because of the
  uniqueness of each ROM
• Second type of ROM is Programmable ROM (PROM)
• The approach allows the user to program small
  quantities using special hardware
• A good idea when only small quantities of the ROM
  are needed
• Third type of ROM is Erasable PROM (EPROM)
• Used when contents of ROM units must change
  periodically
• Use light or electricity to erase and then
  reprogram as needed

38
Read Only Memory

• Can use a ROM to implement any desired
  combinational circuit
• As shown in Chapter 3, a decoder generate 2k
  minterms
• By inserting OR gates to sum the minterms we can
  generate any desired combinational circuit
• The ROM is essentially a decoder with OR gates
  within it
• By leaving the fuses intact for those minterms
  included in the function, the ROM outputs can be
  programmed to represent the Boolean functions of
  the output variables in a combinational circuit

39
ROM Combinational Circuit Example
Design a combinational circuit using a ROM that
accepts a 3-bit number and generates an output
binary number equal to the square of the input
Step 1 Create the truth table for the
combinational circuit
Inputs
Outputs
B5
B4
A2
A1
A0
B3
B2
B1
B0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
0
1
0
0
0
1
0
0
0
1
1
1
0
0
0
0
1
1
0
0
0
0
0
1
0
0
1
1
0
1
1
0
0
0
1
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
1
1
40
ROM Combinational Circuit Example
Design a combinational circuit using a ROM that
accepts a 3-bit number and generates an output
binary number equal to the square of the input
Step 2 Look at the properties of the outputs and
determine if all outputs must be generated by the
ROM
Solution
Inputs
Outputs
B0
B5
B4
A2
A1
A0
B3
B2
B1
B0
B1
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
B2
0
0
1
0
0
0
1
0
0
A0
B3
0
1
1
1
0
0
0
0
1
8 x 4 ROM
A1
1
0
0
0
0
0
1
0
0
B4
1
1
0
1
1
0
0
0
1
A2
B5
1
0
1
0
0
0
1
1
0
1
1
1
0
1
0
0
1
1
B1 is ALWAYS 0
B0 is ALWAYS A0
41
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

42
Programmable Logic Device (PLD)

• An integrated circuit with an array of gates that
  are connected by programming fuses
• Specify the internal logic by table or a list of
  Boolean functions
• Translate the specifications into a fuse pattern
  required to program the PLD
• Three major types of PLDs
• PROM has a fixed AND array (decoder) and a
  programmable OR array
• Programmable Array Logic (PAL) has a fused
  programmable AND array and a fixed OR array
• Programmable Logic Array (PLA) both AND and OR
  arrays are programmable

43
Basic Configuration of PLDs
Outputs
Fixed AND array (decoder)
Fused programmable OR array
Inputs
Programmable Read Only Memory (PROM)
Fused programmable AND array
Fixed OR array
Outputs
Inputs
Programmable Array Logic (PAL)
Fused programmable AND array
Fused programmable OR array
Outputs
Inputs
Programmable Logic Array (PLA)
44
Sequential Programmable Logic Device
Inputs
AND-OR Array (PAL or PLA)
Outputs
Flip-flops
45
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

46
Programmable Logic Array (PLA)

• Similar to the PROM except that the PLA does not
  provide full decoding of the inputs and does not
  generate all possible minterms
• Use a programmable array of AND gates to generate
  minterms
• Connect minterms to programmable array of OR
  gates to generate sum of products expressions
• Use XOR gate on output to choose between F and
  its compliment

47
Example PLA Implementation
A
X Fuse Intact
Fuse Blown
B
C
AB
X
X
X
AC
X
X
X
X
BC
X
X
X
ABC
X
X
X
X
0
X
1
X
Output Functions
F1
F1 ABACABC
F2 ACBC
F2
48
Example PLA Programming Table
Tables consist of three sections product term
list, specification of required input paths,
specification of required output paths
If a variable in the product term appears in its
true form, mark it with a 1. If it appears
complimented, mark it with a zero If it doesnt
appear mark it with a dash (-)
Inputs
Outputs
Product Term
(C)
(T)
F1
F2
A
B
C
AB
1
0
1
1
AC
2
1
1
1
1
BC
3
1
1
1
ABC
4
0
1
0
1
49
Lets look at an example of the PLA design process
Say that we wanted to use a PLA to implement the
following logic functions
F1(A,B,C) ?m(0,1,2,4)
F2(A,B,C) ?m(0,5,6,7)

• We want to obtain a solution that uses the
  smallest PLA
• To get that solution we will want to look at both
  solutions and their complements
• pick the set that minimizes the number of terms
  overall

50
Example 6.2 PLA Implementation
Desired Output Functions
First solve for the solution set that contains
both the function and its complement
F1(A,B,C) ?m(0,1,2,4)
F2(A,B,C) ?m(0,5,6,7)
F1
F2
BC
BC
00
01
11
10
00
01
11
10
A
A
1
1
0
1
1
0
0
0
0
0
1
1
1
0
0
0
0
1
1
1
F1 ABACBC
F2 ABACABC
OR
F1 ABACBC
F2 ABACABC
Next choose the combination that gives the
minimum number of product terms
Choose F1 and F2
51
Example 6.2 PLA Programming Table

• Now Fill in the Programming Table
• If a variable in the product term appears in its
  true form, mark it with a 1.
• If it appears complimented, mark it with a zero
• If it doesnt appear mark it with a dash (-)

Inputs
Outputs
Product Term
(T)
(C)
F1
F2
A
B
C
AB
1
1
1
1
1
AC
2
1
1
1
1
BC
3
1
1
1
ABC
4
0
0
0
1
52
Example 6.2 PLA Implementation
A
X Fuse Intact
Fuse Blown
B
C
AB
X
X
X
X
AC
X
X
X
X
BC
X
X
X
ABC
X
X
X
X
0
X
1
X
Output Functions
F1
F1 ABACBC
F2 ABACABC
F2
53
OVERVIEW

• Introduction
• Random-Access Memory (RAM)
• Memory Decoding
• Error Detection and Correction
• Read-Only Memory (ROM)
• Programmable Logic Device (PLD)
• Programmable Logic Array (PLA)
• Programmable Array Logic (PAL)

54
Programmable Array Logic (PAL)

• The PAL is a programmable logic device with a
  fixed OR array and a programmable AND array
• Easier to program than PLA but not as flexible
  because each OR gate has a limited number of
  minterms it can accommodate
• Connect programmable AND array of minterms to
  non-programmable array of OR gates to generate
  sum of products expressions
• Boolean functions must be simplified to fit into
  one AND-OR section
• Number of product terms in each section is fixed
• May use two OR sections to generate one function
  if too large for one section alone

55
PAL Structure
AND gate inputs
1
2
0
3
4
5
6
7
8
9
Product Term
1
2
F1
3
I1
4
5
F2
6
I2
7
8
F3
9
I3
10
11
F4
12
4 inputs, 4 outputs, 3-wide AND-OR structure
I1
56
PAL Programming Table
Similar programming to PLA table except that
there is an association between the product terms
and the output functions
Inputs
Product Term
Outputs
I1
I2
I3
I4
1
0
1
1
F1 PT1 PT2 PT3
2
1
1
1
3
1
1
4
0
1
1
F2 PT4 PT5 PT6
5
1
1
1
6
1
1
7
0
1
1
F3 PT7 PT8 PT9
8
1
1
1
9
1
1
10
0
1
1
F4 PT10 PT11 PT12
11
1
1
1
12
1
1
57
Lets look at an example of the PAL design process
Say that we wanted to use a PAL to implement the
following logic functions
W(A,B,C,D) ?m(2,12,13)
X(A,B,C,D) ?m(7,8,9,10,11,12,13,14,15)
Y(A,B,C,D) ?m(0,2,3,4,5,6,7,8,10,11,15)
Z(A,B,C,D) ?m(1,2,8,12,13)

• We want to obtain a solution that uses the
  smallest PAL
• To get that solution we will want to each
  function to a minimum number of terms and then
  look for commonality of terms
• Use functions that are subsets of other functions
  if possible and required to reduce the number of
  terms

58
Example PAL Implementation
CD
CD
00
01
11
10
00
01
AB
11
10
AB
00
00
1
01
01
1
11
11
1
1
1
1
1
1
10
10
1
1
1
1
W ABC ABCD
X A BCD
CD
CD
00
01
11
10
00
01
11
10
AB
AB
00
00
1
1
1
1
1
01
01
1
1
1
1
11
11
1
1
1
10
10
1
1
1
1
Z ABCABCDACDABCD
Y AB CD BD
Z W ACD ABCD
59
Example PAL Programming Table
Now complete the programming table
Inputs
Product Term
Outputs
A
B
C
D
W
1
1
1
0
WABC ABCD
2
0
0
1
0
3
4
1
5
1
1
1
XA BCD
6
7
1
0
8
1
1
YAB CD BD
9
0
0
10
1
11
ZW ACD ABCD
0
1
0
12
0
0
0
1
60
Example PAL
AND gate inputs
X Fuse Intact
A
B
A
B
C
C
D
D
W
W
Fuse Blown
61
End Chapter 6