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Lab and Project Assignments

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Describe complete scope setup and threshold assumptions. ... One probe is on a data signal on the DIMM before the series resistor (End closest to DRAM chip) ... – PowerPoint PPT presentation

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Title: Lab and Project Assignments


1
Lab and Project Assignments
2
Lab Assignment Clock skew and jitter measurements
  • Hand PPT lab report.
  • Activities
  • Locate clock probe points on layout.
  • Measures skew (at CPU0, CPU1, both P64H2s, MCH,
    and ICH) and Jitter at MCH.
  • PPT minimum contents
  • Hypothesis What you are measuring and why it is
    important.
  • Results Summary Jitter and Skew
  • Supporting data
  • Illustrate where probes are placed
  • Describe complete scope setup and threshold
    assumptions.
  • Show all clock waveform super imposed on one
    graph.
  • Determine skew from this
  • Show simple jitter (infinite persistence) include
    picture of jitter.
  • Describe issues with this simple jitter method.

3
Project Assignment Simulation to Lab Correlation
  • Goal Tune simulations to measurements
  • Activities
  • Locate DDR signal being probed.
  • Determine all segments and component value.
  • You may need to get component values from
    examining the board.
  • Measure necessary DC voltages
  • Modify the HSPICE DDR template file with actual
    values.
  • Probe points
  • One probe is on a data signal on the DIMM before
    the series resistor (End closest to DRAM chip)
  • The other probe is on a the same data signal at
    the MCH.
  • Capture a read signal at the MCH.
  • Compare measured signal to simulated signal. You
    may need to bring into a spreadsheet and time
    shift data to get to over lap.
  • Adjust elements in the simulation model achieve
    reasonable agreement with measurements. You need
    to define what reasonable is and justify that.
  • PPT minimum contents
  • Hypothesis Simulation model accurately predict
    real circuits.
  • Results Summary
  • Overlay of simulation and measurement waveforms.
  • Overivew of component changes that had the most
    effect on achieving the best results.
  • Supporting data

4
Starter Schematic For DDR Simulation
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