NS9750 - Training Hardware

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NS9750 - Training Hardware
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Memory Interface
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Memory Interface

• Support for SDRAM, asynchronous SRAM, ROM,
  asynchronous flash and Micron synchronous flash
• Support for 8, 16 or 32 bit devices
• Four static memory chip selects and four dynamic
  memory chip selects
• Each chip select can support up to 256MB of
  memory
• Chip selects are independently configured
• Guaranteed 200MB/s BW to/from SDRAM
• 200MB/s is achieved when multiple masters are
  accessing memory and all accesses are row misses
  and all accesses are 8-words.
• Open bank and row status maintained for each
  dynamic memory chip select to maximize system
  performance
• SDRAM refresh cycles performed as needed
• Address mirroring on chip select 1 to support
  boot from flash functionality
• Clock forwarded interface simplifies board design

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Memory Interface Hardware Strapping Pins

• BOOT_STRAP0 (Internal pull-up)
• Chip select 1 byte lane enable polarity select.
  The input is inverted.
• 0 -gt Active low (default)
• 1 -gt Active high
• BOOT_STRAP2 (Internal pull-up)
• Memory interface read mode select.
• 0 -gt Command delay mode.
• 1 -gt This option is not supported.
• BOOT_STRAP43 (Internal pull-up)
• Chip select 1 data width select
• 00 -gt 8 bits
• 01 -gt 16 bits
• 10 -gt 32 bits
• 11 -gt Not Defined

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Memory Interface Hardware Strapping Pins

• GPIO49 (Internal pull-up)
• Chip select 1 polarity. The input is inverted.
• 0 -gt Active low (default)
• 1 -gt Active high
• GPIO44 (Internal pull-up)
• Endian mode. The input is inverted.
• 0 -gt Active low (default)
• 1 -gt Active high
• RESET_DONE (Internal pull-up)
• System Boot mode
• 0 -gt Boot from SDRAM using SPI-EEPROM
• 1 -gt Boot from Flash or ROM (default)

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System Boot from Flash

• NS9750 powers up and the ARM9 is taken out of
  reset.
• The ARM9 begins fetching instructions from
  address 0x00000000.
• This fetch is mirrored from DY_CS_N0 to
  ST_CS_N1.
• The ARM9 configures the memory controller with
  optimal values and disables the address mirroring
  function.
• The ARM9 branches to execute code directly from
  static memory.
• The ARM9 copies the boot code from the static
  memory device to the dynamic memory device.
• The ARM9 branches to execute code out of dynamic
  memory.

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Hints Kinks

• Why must pin boot_strap2 be tied low ?
• Command delayed mode was implemented. Clock
  delayed mode is reserved for future use.
• How may devices can be attached to the system
  memory bus ?
• At 100Mhz, the memory interface pins can drive 2
  loads, typically a flash and an SDRAM or a buffer
  and an SDRAM. Other configurations at lower clock
  rates must be verified with a Spice analysis.
• Why must pin clk_out0 be connected to pin
  clk_in0 ?
• This is the SDRAM feedback clock path. It is used
  to clock the read data into the chip. The other
  three feedback clocks, clk_in31, need only be
  connected to ground.
• Can I add delay to the feedback clock path ?
• No. The feedback clock path should be no longer
  than 2 inches.
• What is the speed of the memory interface clock ?
• The memory interface clock is always the same
  frequency as the AHB clock. Refer to the SCM
  chapter for complete details.

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Hints Kinks

• What are some example part numbers ?
• Micron 128Mb SDRAM MT48LC4M32B2
• Micron 8Mb Flash MT28F800F3
• Where can I find component specifications?
• http//www.micron.com/
• http//www.intel.com/

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Example Memory Subsystem
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Example SDRAM Burst Read
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Example Flash Read