???-210: S?ed?as

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???-210 S?ed?asµ?? ??f?a??? S?st?µ?t???e?µe????
???µ??? 2008

• VHDL ??a S?ed?asµ?????????a??? ?????µ?t??

??d?s???sa ?a??a ?. ???a??
?a?ep?st?µ?? ??p??? ?µ?µa ??e?t??????? ???a?????
?a? ???a????? ?p?????st??
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?e??????

• VHDL Processes
• ??t???? If-Then-Else ?a? CASE
• ?e????af? Flip-Flop µe VHDL
• ?e????af? ????????a??? ?????µat?? (ß?se?
  p??a?a/d?a???µµat?? ?atast?se??) µe VHDL
• S???????sµ?? µeta?? Processes

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VHDL Process

• ??a s????? ap? e?t???? VHDL t? ?p??? e?te?e?ta?
  ?ta? ??a signal (ap? ??a s???e???µ??? s?????)
  a????e? t?µ?.
• ? ???µ?? (body) e??? process ???p??e? ??a
  se???a?? (sequential) p????aµµa, d??. ?? t?µ??
  t?? signals a?a?e????ta? µ??? ?ta? ?????????e? ?
  e?t??es? t?? p?????µµat??.
• ?p??e? ep?s?? ?a ???s?µ?p???se? variables, t??
  ?p???? ? t?µ? a?a?e??eta? aµ?s??.

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????te?t????? VHDL
architecture name_arch of name is begin
end name_arch
Signal/Variable declaration Component declaration
?? ???e process pe????e? a???????a??? e?t????
(sequential statements), a??? ??a ta processes
e?te????ta? ta?t?????a
?a?t?????e? e?t???? (concurrent statements)
Process 1
?a?t?????e? e?t???? (concurrent statements)
Process 2
?a?t?????e? e?t???? (concurrent statements)
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VHDL Process
P1 process (ltsensitivity listgt) ltvariable
declarationsgt begin ltsequential
statementsgt end process P1

• ??sa se ??a process
• ????es? µetaß??t?? (variables)
• µe ?a? ?µes? e??µ???s?.
• ????es? s?µ?t?? (signals) µe lt ?a? ?
  e??µ???s? ???ete st?
• t???? t?? process.

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Signals Vs Variables se ??a Process

• Te??e?ste ?t? A, B, ?a? C e??a? a???a??? µe A1,
  B5, ?a? C10.
• A, B, C signals A, B, C variablesbegin
  process begin process B lt A B
  AC lt B C B end
  process end process B 1 ?a? C 5 B
  1 ?a? C 1( ???s?µ?p??e? t?? ( ???s?µ?p??e?
  t??
• a????? t?µ? t?? ??a t?µ? B (5)
  ?ta? t?? B (1) ?ta? ?p??????e? t? C )
  ?p??????e? t? C )

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??t??? If-Then-Else

• if_label
• if boolean_expression then
• sequential_statement
• elsif boolean_expression then
• sequential_statement
• else
• sequential_statement
• end if if_label
• S?µßas?
• -- p??a??et???
• epa?????? d??at?

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??t??? CASE

• case_label
• case expression is
• when choice gt sequential statement
• when others gt sequential statement
• end case case_label

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?e????af? Flip-Flop µe VHDLTet???
??µ?p???d?t??µe?? D-FF µe ?s??????? ??????p???s?

• ????s? ??t?t?ta?
• -- Positive Edge-Triggered D Flip-Flop with
  Reset
• -- VHDL Process Description
• library ieee
• use ieee.std_logic_1164.all
• entity dff is
• port(CLK, RESET, D in std_logic
• Q, Q_n out std_logic)
• end dff

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?e????af? Flip-Flop µe VHDLTet???
??µ?p???d?t??µe?? D-FF µe ?s??????? ??????p???s?

• ????te?t?????
• architecture pet_pr of dff is
• -- Implements positive edge-triggered bit state
  storage
• -- with asynchronous reset.
• signal state std_logic
• begin
• Q lt state
• Q_n lt not state
• process (CLK, RESET)
• begin
• if (RESET '1') then
• state lt '0'
• else
• if (CLK'event and CLK '1') then
• state lt D
• end if
• end if
• end process
• end pet_pr

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????????a?? ?????µa se VHDL?????e?t?? ????????a?

• T?µ??e?te t? pa??de??µa t?? a????e?t? t??
  a???????a? 0101, µe µ?a e?s?d? (X) ?a? µ?a
  ???d? (Z).
• ?????aµµa ?atast?se??

?
?
C
D
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?????e?t?? ????????a? se VHDL (s??.)

• ???s?µ?p????µe 3 ?e????st? processes, ta ?p??a
  e?te????ta? pa??????a.
• ? s???????sµ?? µeta?? t?? d?af???? processes
  ep?t?????eta? ap? t?? a?????ep?d?as? ??????
  signals.
• 3 processes
• St???e?a ???µ?? (storage cct) state_register
• ?????? ??s?d?? FFs (next state logic)
  next_state_func
• ?????? ???d?? (primary output logic)
  output_func

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?????e?t?? ????????a? se VHDL (s??.)

• ??????µe ??a scalar enumeration type ??a
  a?apa??stas? t?? 4?? ?atast?se??
• type state_type is (A, B, C, D)
• ?????????, d??????µe signals ? variables ??a t??
  pa???sa ?a? t?? ep?µe?? ?at?stas?
• signal state, next_state state_type
• state ?a? next_state µp????? ?a p????? µ??? t??
  t?µ? A, B, C, ? D. ???sp??e?a a???es??
  ?p??asd?p?te ????? t?µ?? ?a d?se? ????? st??
  s?µß???µet?f?as?.

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????s? ??t?t?ta? ????te?t??????

• -- Sequence Recognizer VHDL Process Description
• library ieee
• use ieee.std_logic_1164.all
• entity seq_rec is
• port(CLK, RESET, X in std_logic
• Z out std_logic)
• end seq_rec
• architecture process_3 of seq_rec is
• type state_type is (A, B, C, D)
• signal state, next_state state_type
• begin
• end

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Process ??a St???e?a ???µ?? (State Register)

• -- Process 1 - state_register implements
  positive edge-triggered
• -- state storage with asynchronous reset.
• state_register process (CLK, RESET)
• begin
• if (RESET '1') then
• state lt A
• else
• if (CLK'event and ClK '1') then
• state lt next_state
• end if
• end if
• end process
• ??sa FFs ??a?t?ta? ap? t?? a???µ? t?? t?µ?? p??
  µp????? ?a p????? ta signals state next_state!
  G?a a?t? t?? pe??pt?s?, ?p?????? 4 d??at??
  ?atast?se?? (A, B, C, D) ?a?, ep?µ????, ?a
  ???s?µ?p??????? 2 FFs.

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Process ??a S??a?t?se?? ?p?µe??? ?at?stas?? (Next
State Functions)

• -- Process 2 - next_state_function implements
• -- next state as function of input X and state.
• next_state_func process (X, state)
• begin
• case state is
• when A gt
• if X '1' then
• next_state lt B
• else
• next_state lt A
• end if
• when B gt
• if X '1' then
• next_state lt C
• else
• next_state lt A
• end if
• when C gt
• if X '1' then

???a?a? ?atast?se??
next_state next_state Z Z
state X1 X0 X1 X0
A B A 0 0
B C A 0 0
C C D 0 0
D B A 1 0
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Process ??a S????t?s? ???d?? (Output State
Function)

• -- Process 3 - output_function
• -- implements output as function of
• -- input X and state.
• output_func process (X, state)
• begin
• case state is
• when A gt
• Z lt '0'
• when B gt
• Z lt '0'
• when C gt
• Z lt '0'
• when D gt
• if X '1' then
• Z lt '1'
• else
• Z lt '0'
• end if
• end case

?p???e? µ??t??? Mealy
???a?a? ?atast?se??
next_state next_state Z Z
state X1 X0 X1 X0
A B A 0 0
B C A 0 0
C C D 0 0
D B A 1 0
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S???????sµ?? µeta?? t?? processes

• state_register process (CLK, RESET)
• state a?a?e??eta? ß?se? t?? CLK ?a? RESET
• next_state_func process (X, state)
• next_state a?a?e??eta? ß?se? t?? X ?a? state
• output_func process (X, state)
• Z a?a?e??eta? ß?se? t?? X ?a? state

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S???????sµ?? (s??.)

• Te??e?ste t?? a??????? pe??pt?s?

?????? t0 ?????? t1 ?????? t2
state D X0 X1
X1
Z1 next_state A next_state ?
RESET0 Z0 Z?
CLK0 RESET0 RESET0
CLK0 CLK0
???s?µ?p??e? t?? t?µ?? t?? state ?a? X st?? ?????
t0 ??a ?a ?p?????se? t? next_state
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S???????sµ?? (s??.)

• Te??e?ste t?? a??????? pe??pt?s?

?????? t0 ?????? t1 ?????? t2
state D X0 X1
X1
Z1 next_state A next_state A
RESET0 Z0 Z0
CLK0 RESET0 RESET0
CLK0 CLK0
???s?µ?p??e? t?? t?µ?? t?? state ?a? X st?? ?????
t0 ??a ?a ?p?????se? t? next_state af?? CLK ? ?