HiSIM: Hierarchical InterconnectCentric Circuit Simulator

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HiSIM Hierarchical InterconnectCentric Circuit
Simulator

• Tsung-Hao Chen Synopsys Inc.
• Jeng-Liang Tsai UW-Madison
• Charlie Chung-Ping Chen GIEE NTU

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Outline

• Introduction
• Reluctance extraction and simulation
• Preconditioned iterative methods for power-grid
  analysis
• Substrate/power-grid co-analysis
• Reluctance-enhanced model order reduction
• Interconnect-centric nonlinear circuit simulation
• Macro-modeling technique and hierarchical
  analysis
• Partitioned explicit method
• Summary

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Motivation

• Power delivery noises (IR drop, Ldi/dt drop) are
  getting significant
• Increasing power(current) consumption
• Decreasing supply voltage (smaller noise margin
  budget)
• Need to perform signal/power integrity analysis
• Interconnect-centric large of linear elements

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Signal/Power Integrity Analysis Issues

• Signal/power integrity problems are analog
• Switch-level analysis may not be satisfactory
• SPICE-level accuracy simulation is required
• Large-scale, or chip-level simulation is needed
• Size matters
• Millions-billions of passive and active devices
• SPICE simulation is slow and memory inefficient
• SPICE3 DC analysis (nodegt10,000) several hours
• How about node gt millions?
• Efficient and accurate chip-level
  interconnect-centric analysis methods are
  important.

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Power-delivery Noises Cause Timing Uncertainty

• Timing is important for some circuits
• Clock skew uncertainty caused by IR-drop
• I/O pad timing uncertainty from simultaneous
  switching

Clock simulation with dynamic IR-drop R. Saleh,
et al, 2000
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Timing Also Induces Noises

• Timing also induces power fluctuation noises
• Drivers are nonlinear
• Decoupled linear/nonlinear methods lose timing
  information
• Need
• efficient and accurate
• interconnect-centric
• nonlinear circuit simulation
• methods

Source Intel Journal
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Interconnect-Centric Circuit Analysis

• Timing information are important for some
  applications
• Need to include nonlinear device models
• e.g. clock-tree and power-grid co-analysis
• Interconnect centric

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Computation Cost of Nonlinear Simulation

• Nonlinear simulation
• performs Newton-Raphson for each time-step
• each NR iteration has to LU once
• Runtime ? of NR iterations ? cost of LU
• Reduce the cost of LU
• Flat analysis does LU to the whole system
  (linear nonlinear)
• Objective circuit contains largenumber of linear
  elements
• Only nonlinear elements change for each NR
  iteration
• Temporal latency

Transient simulation flow
Newton-Raphson
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Macromodeling and Hierarchical Analysis

• Build macromodels for all sub-circuits
• Combine macromodels and form a smaller system
• Only build macromodels for linear sub-circuits
  once
• No need to rebuild nonlinear macromodels if port
  voltage doesnt change

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Realization in Matrix

• Macromodeling by LU(or Cholesky) decomposition
• Combine macromodels and form a smaller matrix

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Runtime Comparison

• Benefit from temporal latency

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Concept of Partitioned Explicit Method

• Explicit predictor and iterative corrector
• Original NR LU(AB)
• New method LU(A)
• We prove the convergence condition.
• Simulation result shows 2-3 steps to converge

i
i
Nonlinear, A
Nonlinear, A
After correction
Linearization Ai
xi1
xi1
Linear prediction
xi
xi
Linear, B
Linear, B
Linearization Ai
v
v
ith iteration of NR
Predictor and corrector
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Realization Partitioned Explicit Method

• Partition circuit into linear and nonlinear parts
• Phase 1 Fix the port current
• Phase 2 Fix the port voltage

Original system
Partitioned explicit method
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Runtime Comparison

• Clock-tree and power-grid co-analysis
• 180x faster than flat simulation

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Backup Slides
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Computation Cost Reduction

• Flat analysis
• has to perform LU for the whole matrix in every
  NR iteration.
• Hierarchical analysis
• Linear sub-circuits
• only has to perform LU once, and
• reuse macro-models in every NR iteration
• Nonlinear sub-circuits
• check port voltages
• Reuse macro-models if no changes
• Benefit from temporal latency