A DFT Method for Time Expansion Model at Register Transfer Level

1
A DFT Method for Time Expansion Model at
Register Transfer Level

• Hiroyuki Iwata, Tomokazu Yoneda and Hideo
  Fujiwara
• Nara Institute of Science and Technology

2
Outline

• Background
• Previous DFT Methods
• Strong Testability
• Proposed Method
• Partially Strong Testability
• Experimental Results
• Summary

3
Background
n

• Sequential test generation
• complexity very high
• Full scan DFT
• Decreases the complexity
• Advantages
• fault efficiency complete
• test generation time short
• Disadvantages
• test application time long
• at-speed testing difficult

2k
n
k number of FFs n combinational part of
a circuit
Sequential ATPG
n
Full scan DFT
The size for test generation
4
Previous Works

• RTL non-scan DFT methods
• RTL datapath non-scan DFT
• Dey et al. 1996
• Norwood et al. 1996

• RTL controller-datapath
• Ghosh et al. 1998
• Ohtake et al. 2000

5
Non-Scan DFT method for RTL Controller-Datapath
Circuits Ohtake et al. 2000
PI
Test Controller
PI
PI
Controller Ohtake et al. 1998
Datapath Wada et al. 1999
Control signals

Status signals
PO
PO

• Controller Invalid state generator (ISG)
• Datapath strong testability
• Test controller inserted to test the controller
  andthe datapath independently

6
Strong Testability (1/2)

• Strong Testability Wada et al.
• Based on hierarchical test generation
• Test generation for each module
• Test plan generation
• A datapath is said to be strongly testable if
  there exists a test plan (a sequence of
  control vectors) for each hardware element m

PI
PI
m
Control input
Control Vector
PO
Datapath
7
Strong Testability (2/2)

• DFT method Wada et al.
• Each hardware element satisfies the following
  conditions
• any pattern can be applied from PIs
• any response can be observed from POs
• Large Hardware overhead
• more than necessary to achieve complete fault
  efficiency

vany value
PI
PI
v
v
Thru function
Thru function
v
v
m
Control input
v
Thru function
v
PO
Datapath
8
Research Objectives

• High fault efficiency
• Low hardware overhead
• Short test application time
• At-speed testing

9
Basic Idea of the Proposed Method
n
n
d
n
m
2k
n
n
m number of gates of a module
d number of registers
k number of FFs
n number of gates of a circuit
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Partially Strong Testability (1/2)
Thru function
dont care
PI2
v
v
MUX
PI1
v
PI1
v
v1
v
PO
v
v
PI
m
m
Time Expan-sion
PI2
m
m
v
v1
PI2
v
v2
v
v
m
m
PI2
MUX
MUX
v
v2
v
v
MUX
PO
PO
PO
v1,2any value in the range ( the values which
appear in normal operation )
vany value
Time expansion model

• Partially strong testability
• Thru function is not needed to set any value in
  the range

• Strong testability
• Thru function is needed to propagate any value

11
Partially Strong Testability (2/2)

• Partially strong testability
• Theorem The number of time frames is bounded by
  a linear function of the number of registers
• Condition For each loop c , partially strong
  testable path pc exists in an RTL circuit CD
• pc satisfy the following conditions
• vn can be propagate from a PI to a hardware
  element
• Any response of a hardware element can be
  propagated to a PO

PI
pc
v1
v5
loop c
v2
mcin
v3
v4
v6
v17any value in the range of each signal line
PO
v7
12
Partially Strong Testable Path
PI
v1
pc
C1
PI
v1
v2
x
C1
mcin
v1
PI
v3
v5
C1
C2
loop c
v2
mcin
v4
C3
v6
Time Expansion
C3
C3
C4
v3
v5
C2
v2
PO
v4
mcin
v3
C2
v6
v17any value in the range of each signal line
v6
C4
C4
x dont care
PO
PO
v7

• Control path vn can be propagated from a PI to
  a hardware element
• Observation path vn can be propagated from a
  hardware element to a PO

13
Flow of the Proposed Method
A controller-datapath circuit
1. Control Paths Construction
DFT
A partially strong testable circuit
2. Observation paths Construction
3. Test Controller Generation
TEM generation
A time expansion model of the partially strong
testable circuit

• Control paths and observation paths for each
  hardware element include partially strong
  testable paths for each loop
• Partially strong testable

Combinational test generation
Test patterns for a partially strong testable
circuit
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DFT Example
Required Control signals
1. Control Paths Construction
2. Observation paths Construction
1
3. Test Controller Generation
PI1
PI2
PI3
reg1
T output pattern of the CL
t2
0
m2
1
1
t1
0
m1
d1
SUB
sreg
ADD
m4
0
TC
CL
reg2
reg3
0
0, 1
m3
PO1
PO2
OMUX
Controller
Datapath
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Test Generation Method
x dont care
X
TC
X
-3
m1
X
ADD
Time Expansion
OM
X
-2
m3
X
TC
X
X
m1
SUB
PI1
PI2
PI3
ADD
OM
m4
reg1
m3
-1
X
TC
t2
m2
SUB
t1
m1
d1
OM
SUB
m4
sreg
X
ADD
m3
0
m4
X
TC
TC
CL
reg2
reg3
OM
m3
Time expansion model for the subtracter
PO1
PO2
OMUX
Controller
Datapath
16
Test Generation Method
x dont care
X
X
TC
X
t2
X
-4
t1
OM

• TEM Generation
• TEM is generated so that hardware elements which
  exist on loops should not appear as possible
• Control paths and observation paths for each
  hardware element are included in the generated
  TEM
• Test Generation for the TEM
• Combinational ATPG is applied
• Generated test patterns are converted to test
  sequences

X
TC
X
-3
m1
X
t2
X
ADD
t1
OM
X
-2
m3
X
TC
X
m1
SUB
t2
X
ADD
t1
OM
m4
m3
-1
CL
TC
m2
m1
SUB
t2
ADD
t1
OM
m4
m3
0
CL
TC
t2
t1
OM
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Experiments
Circuit characteristics

• Subjects of comparison
• Original Circuit(Sequential ATPG)
• Full scan method
• Strongly testable method Ohtake et al. 2000
• Proposed method
• Points of comparison
• Hardware overhead
• Fault efficiency
• Test generation time
• Test application time

Synthesis tool AutoLogic II Mentor
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Hardware Overhead
ST Strongly testable method Ohtake et al. 2000

• The hardware overhead of the proposed method is
  much smaller than that of others

19
Test Generation Results
ST Strongly testable method Ohtake et al. 2000
Test generation tool TestGen Synopsys

• The proposed method can achieve 100 fault
  efficiency, except RISC, in practical test
  generation time

20
Test Application Time
ST Strongly testable method Ohtake et al. 2000

• The proposed method can achieve much shorter test
  application time compared to the full-scan method

21
Summary

• Proposed Method
• Partially strong testability for RTL
  controller-datapath circuits
• Hardware overhead and test application time are
  improved at the cost of some test generation time