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Implicit Enumeration of Structural Changes During Circuit Optimization

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Number of rewiring subsets to try is exponential! ... Implement the logic using constructive timing-driven decomposition. Accept or restore the change ... – PowerPoint PPT presentation

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Title: Implicit Enumeration of Structural Changes During Circuit Optimization


1
Implicit Enumeration of Structural Changes During
Circuit Optimization
  • Victor N. Kravets

Prabhakar N. Kudva
IBM TJ Watson Research Center Yorktown Heights, NY
June 9, 2004
2
Overview
  • Motivation
  • Circuit restructuring approach
  • Symbolic formulation
  • Experimental results
  • Conclusions

3
Motivation
Timing optimization in the high performance
physical synthesis flow
4
Physical Domain Optimization Challenges and
Requirements
Challenges
  • Limited free space to place new logic
  • Pronounced technology-specific effects
  • interconnect delay
  • wiring congestion

5
Existing Resynthesis Alternatives
  • Collapse/re-decompose/re-map circuit regions
  • Scrambles good portions of design
  • Limits timing improvements
  • Localized transformations
  • Dont cares optimization
  • Considers global functional properties
  • Difficult to use in practice
  • Re-wiring techniques
  • Explores functional equivalence of signals
  • Requires what if analysis for each rewiring
    change

6
Highlights
  • New restructuring technique
  • rewiring change
  • logical change
  • Implicit computation and compact representation
    of choices
  • Application to high performance physical
    synthesis

7
Combining Rewiring and Logical Change
x
x
y
y'
h(y)
  • The transformation changes h and its support
  • Circuit functionality preserved

8
Rewiring Change
Can y1 and y2 replace fanin of h?
x1
x2
x3
x4
x1
x2
x1
x2
y1

g1(x)
y2
g2(x)
f(x)
9
Logic Change
x1
x2
x3
x4
Choices for h
x1
x1
x2
x2
y1
y2
f(x)
10
Rewiring Choices
What are the feasible subsets of rewiring
candidates?
  • Number of rewiring subsets to try is exponential!
  • BDDs have very compact representation of rewiring
    subsets

11
Implicit Computation of Rewiring Choices
yi
yn
si
y1
s1
sn
yi connects to rewired logic iff si1
Parameterize
12
Feasible Rewiring Subsets
Compact representation of rewiring choices for h
Solution counts for h
Original circuit
Number of solutions
Fanin of size h
1 2 3 4 5 6 7 8 9 10 11 12 13
0 2 39 257 799 1406 1599 1263 713 286 78 13 1
13
Examining Restructuring Choices
  • For a given gate compute symbolic representation
    of its rewiring choices
  • Given fanin size k, select a rewiring
  • Establish fanin connections to the changing logic
  • Derive function of changed logic
  • Implement the logic using constructive
    timing-driven decomposition
  • Accept or restore the change

14
Early Synthesis Timing Improvement
  • Average of 18 in area saving, in addition to the
    delay improvements

15
Placement-Driven Restructuring ASIC Example
Slack without the restructuring -0.095
Slack with the restructured logic 0.061
16
Conclusions
  • New symbolic formulation for circuit
    restructuring
  • Emphasizes rewiring change, circuit structure
  • Incremental ability to improve design makes it
    suited in late synthesis
  • Implemented in the timing closure loop within
    high performance synthesis flow
  • Experimental results show practical value of the
    restructuring technique
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