Analysis of a Parallel FPGA design of a CFAR processor

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Analysis of a Parallel FPGA design of a CFAR
processor
V.A Kyovtorov
supported by the Bulgarian National Science Fund
under Grant DO-02-344/2008
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Parallel FPGA design of a CFAR.
A typical detection process
Detection Decision Making
Square Law detector
Decimation and filtering
A/D convertion
correlator
CFAR
frequency band of 500MHz a sampling rate of at
least 1Gsps
16bit -gt system throughput 16Gbis/s.
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Parallel FPGA design of a CFAR.
The problem
The contemporary radar and communication signal
processing requirements pose very high
computational performance demands for the real
time signal processing. For example, a
contemporary input signal frequency band of
500MHz needs a sampling rate of at least 1Gsps
or, if we assume 16bit data samples, the system
throughput reaches 16Gbis/s. Solutions
buffering fast computational units efficient
parallel structures
The purpose of this work is to propose a
performance efficient reconfigurable hardware
CFAR structure, to study the possibilities to
parallelise the CFAR algorithm and to reveal the
dependences between the algorithm
parallelisation, power consumption and the
speedup.
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Constant False Alarm Ratio Algorithm
Parallel FPGA design of a CFAR.
xz
CA-CFAR algorithm
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Proposed Parallelization
Parallel FPGA design of a CFAR.
Two parallel CA-CFAR computational structure
An example of two parallel CA-CFAR sliding
windows
K- sliding CFARs working in parallel
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Applied to the signal
Parallel FPGA design of a CFAR.
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Parallel FPGA design of a CFAR.
Hardware Data Structure
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Parallel FPGA design of a CFAR.
Main Technology

• TECHNOLOGY
• VIRTEX II PRO, 60MHz Clock
• Tested devices XC2VP2-7fg256
  XC2VP30-7ff1152 XC2VP70- 7ff1517
• Xilinx ISE
• Modelsim
• MATLAB
• Xilinx XPower Analyzer
• Altera Stratix II
• Quartus II 9.0
• XPower Analyser/ PowerPlay Power Analyzer

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Parallel FPGA design of a CFAR.
Experimental Results
Data Input 16bit
algorithm verification procedure
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Parallel FPGA design of a CFAR.
Experimental Results
The throughput eq. for 16 bit data input
f is the maximal frequency according to the
Xilinx ISE synthesis tool, k-the number of
parallel CA-CFAR structures
The maximal throughput for XC2VP30, XC2VP70 and
XC2VP2, acc. to Xilinx ISE tool
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Parallel FPGA design of a CFAR.
Utilization, acc. to Xilinx ISE tool
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Parallel FPGA design of a CFAR.
Utilization, acc. to Altera Quartus 9.0
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Parallel FPGA design of a CFAR.
Total Power Estimation
Clock frequency 60Mhz

• Altera response, Stratix II technology
• Default toggle rate I/O signals 50
• Remaining signals vectorless estimation

Total power consumption for XC2VP2, XC2VP70 and
XC2VP30 as a function of k
Increasing the number of parallel structures
leads to increased number of buffers and
interconnects. The signals fanout dramatically
increases after a certain point, which costs
extra power.
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Parallel FPGA design of a CFAR.
Some frequency reports

• Maximal reported frequency
• Virtex II Pro 60MHz
• Virtex IV 100MHz
• Stratix II 164MHz
• Stratix III gt 164MHz

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Parallel FPGA design of a CFAR.
Conclusions

• The design utilization is linear as a function of
  the k- number parallel structures and is
  identical for the tested devices from the
  considered VIRTEX II PRO technology.
• The throughput grows linearly with the number of
  parallel CFAR units.
• A single CFAR implementation utilizes 1.4 of the
  VIRTEX II Pro XC2VP30 chip, providing a
  throughput of 974 Mbps.
• 32 parallel CA-CFARs provides 37.5 utilization
  and throughput 31Gbps for the same XC2VP30 chip.
• k - full parallelised algorithm, k -linear
  utilization and speedup has been demonstrated.
• In this design, using two separate (smaller) FPGA
  chip for a 18th parallel CFAR implementation
  could be more efficient than a single larger one.
• Xilinx Virtex Technolgy - After 18 parallel
  CA-CFARs (k18) the dynamic power consumption
  increases dramatically - above 750.
• The signals fanout dramatically increases after a
  certain point, which costs extra power.
• Considering the particular implemented algorithm,
  Altera Technology reveals better dynamic power
  consumption and frequency possibilities than
  Xilinx Virtex Technolgy

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Parallel FPGA design of a CFAR.
Remarks and future research
Black box - Xilinx ISE / Quartus II 9.0 -XPower
Analyser/ PowerPlay Power Analyzer
Acknowledgements Gratitude to Georgi Gaydadjiev,
Georgi Kuzmanov, Pavel Zaykov, Chunyang Gou, Yao
Wang, Catalin Ciobanu, Laiq Hasan, for the help
and the constructive discussions
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