A BS test controller model

1
A BS test controller model

• J. M. Martins Ferreira
• FEUP / DEEC - Rua Dr. Roberto Frias
• 4200-537 Porto - PORTUGAL
• Tel. [phone] / Fax [phone]
• (jmf_at_fe.up.pt / http//www.fe.up.pt/jmf)

2
Objectives

• To identify what are the main information sources
  required to enable test program generation for BS
  boards
• To present a formal (yet simple) specification
  language that enables the student to write test
  programs for real case studies

3
Outline

• Basic test operations
• To control the BS infrastructure
• To synchronise the BS infrastructure with
  external test resources
• To control internal test resources and test
  program flow
• The test instruction set for each type of basic
  test operations
• Test program generation

4
BS infrastructure (1)

• Apply a TCK cycle while TMS is fixed at a
  pre-defined (0 or 1) logic value
• Shift a bit stream into the selected scan chain,
  without comparing the bits shifted out with any
  expected responses (the TMS line must be held at
  0 except in the last TCK cycle, when it must be
  held at 1)

5
BS infrastructure (2)

• Shift a bit stream into the selected scan chain,
  while the bit stream shifted out is checked
  against expected values in pre-defined bit
  locations (the TMS line must be held at 0 except
  in the last TCK cycle, when it must be held at 1)
• Apply N TCK cycles while TMS is held at 0
• Select the BS chain in which the following test
  operations are to take place

6
Synchronisation

• Set the synchronisation output to a pre-defined
  logic value (0 or 1)
• Wait until the synchronisation input is set to a
  pre-defined logic value (0 or 1)

7
Internal resources / test flow

• Load an internal counter with the required number
  of TCK cycles
• Select the error flag to be set if an expected
  value is not found
• Perform a conditional jump in the test program
  flow according to the value of the selected error
  flag
• Conclude the test program

8
BS infrastructure
9
The NSHCP instruction

• NSHFCP 5500H,0309H,0F0FH
• NSHFCP vector,expected,mask
• Shifts in a test vector that forces the last 8
  cells (8..15) to 10101010 and all the first 8
  cells (0..7) to 0
• Checks that cells (0..3) capture 1001 and cells
  (8..11) capture 1100

10
Synchronisation
11
Internal resources / test flow
12
Test program generation

• The low abstraction level of the proposed
  instruction set makes manual test program
  development tedious and error-prone
• It is highly desirable to have an automatic test
  program generation tool
• However, our pedagogical objective would not be
  achieved if the small details of controlling the
  BS chain at bit-level were omitted