ELEC-7250%20VLSI%20Testing

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ELEC-7250 VLSI Testing

• Scan Design Implementation on ISCAS 89 Benchmark
  Circuits s1423 and s1512
• Completed by
• Jonathan Harris

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What is Scan Design?
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Scan Design Pros Cons

• Disadvantages
• Gate and area overhead
• Performance penalty 2 gate delays
• Long test application time

• Advantages
• High Fault Coverage
• Minimal Test Generation Time
• Easily Automated

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s1423 and s1512
s1423 s1512
Primary Inputs 17 29
Primary Outputs 5 21
Gates 557 780
Flip-Flops 74 57
Scan Overhead 22.8 16.9
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Scan Design Results
Total Faults Undet. Faults Fault Coverage Gates Test Time (min)
circuit s1423
w/o scan 1663 946 47.78 731 19
pseudo-scan 1663 27 98.38 731 32
full scan 2131 27 98.73 1027 726
circuit s1512
w/o scan 1411 1364 22.86 837 14
pseudo-scan 1411 68 95.18 837 23
full scan 1761 68 95.14 1025 487
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Project Demo and Questions