ENGR 330: Today

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ENGR 330 Todays Class

• Toys, er, Processor Technology
• Cache Review
• Magic fully associative cache
• Four Questions/3 Cs
• Virtual Memory
• Toys!

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Processor Technology

• Tubes fragile!
• Transistors big, but promising
• ICs thank goodness for DIPs
• Sorry, no first-aid kit

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Direct Mapped Cache

• The basis of todays designs
• A collection of high speed RAM locations
• Broken into individually addressed cache
  entries
• Part of RAM address chooses cache entry (Direct
  mapping)
• A cache entry
• Index is its address in the cache
• Valid bit - true if the entry contains valid RAM
  data
• Tag holds the address bits not matching the
  cache address
• Data area - where the stored data resides
• Store multiple words (spatial locality)

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Set Associative Caches

• That 2-way, 4-way, 8-way stuff
• Provides multiple hit entries per mapping
• Problem
• Calculate size information for a set associative
  cache
• Attributes
• Address size
• Block size
• Number of lines
• N-way

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Fully associative cache

• Association list approach
• Accepts an address
• Returns the data
• Not a RAM stores tags and data
• Tag field full address block size
• Data field data block
• Parallel tag field checking
• Automatically matches, retrieves data with
  matching tag
• Expensive in terms of logic

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Four Questions

• General framework for memory hierarchies
• 1. Where can a block be placed?
• Different schemes have different restrictions
• Some have no restrictions (fully associative)
• 2. How is a block found?
• Fully associative - logic does all the work in
  one cycle
• Direct addressing does much of the work
• 3. How do we choose a block to replace?
• Option Randomly
• Option LRU
• 4. What happens during a write?
• Write-back
• Write-through

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Types of Misses (Three Cs)

• Compulsory misses or Cold start misses
• When a block is first accessed by the program
• Impossible to eliminate these
• Right block size can reduce the number
• Capacity misses
• Cache cant contain all blocks needed by the
  program
• i.e. the program keeps pulling blocks back in
  after theyve been replaced by other referenced
  blocks
• Suggests the cache isnt big enough
• Conflict misses or Collision misses
• When multiple blocks compete for the same
  set/location
• Happens in set associative and direct mapped
• Doesnt happen in fully associative cache

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Virtual Memory (VM)

• The Cache problem
• Convert a RAM address into a data item
• The VM problem
• Convert a convenient RAM address into the real
  one
• Back to the old problem Software is expensive
• Eliminate trouble caused by varying RAM addresses
• How do we load a program into RAM?

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Memory Management Problems

• Relocation
• Storage Protection
• Fragmentation

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Assumptions

• User applications pose the biggest problems
• Memory Management focuses on user mode
• User programs run in restricted RAM
• Restrictions may be turned off for the OS
• I/O operations use real addresses

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1 BaseLimit Register

• Memory controlled through 2 registers
• Base register sets programs starting address
• Limit register sets programs address space
  size
• All of the programs addresses are relocated
• If greater than limit, then an error
• Add base value to get real RAM address
• Program cant see RAM outside its area

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2 Segmentation

• Similar to 80x86/Pentium segments
• Generalization of BaseLimit
• A set of registers tied to high address bits
• High bits select a segment register set
• Rest of address is processed like BaseLimit

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Fragmentation problems

• External fragmentation
• Internal fragmentation

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3 Paging

• All segments are the same (small) size
• Minimizes the fragmentation problem
• 4K for example
• So we dont need a limit register
• Addresses translated with a page table
• High order bits select the page table entry
• The selected entry points to the page in RAM
• Low order bits are the offset into the page
• CPU must support paging
• Special register points to the current page table
• Gets changed when switching processes

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Virtual Memory

• Uses RAM as a cache
• Real data is all on the hard drive
• Pages travel to RAM from hard drive as needed
• Pages sent to hard drive if not being used
• Page table entry (PTE) indicates options
• Page is in RAM right now (valid)
• Page is not in RAM, but on the hard drive
• Page doesnt exist
• Other PTE info
• Page has been used/read
• Page is read only
• Page is dirty

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Implications of Paging

• Good things
• Programs can be larger than physical RAM
• Programs cant see each others RAM
• Bits of RAM can be shared through mapping
• Problems
• Thrashing and working sets
• Slow translation speeds Translation Lookaside
  Buffer (TLB)
• Yet another specialized sort of cache

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Page system sizing questions

• Size of the page table, given
• 4K pages
• 24-bit virtual addresses
• 32-bit physical (real) RAM addresses
• 4 bits for valid, dirty, protected, used
• Size of the page table, given
• 8K pages
• 32-bit virtual addresses
• 36-bit physical (real) RAM addresses
• 4 bits for valid, dirty, protected, used

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More toys?

• Magnetic storage
• Hard Drives

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Thats it.

• Questions?
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