COMP 206: Computer Architecture and Implementation

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COMP 206Computer Architecture and Implementation

• Montek Singh
• Wed., Sep 25, 2002
• Topic Instruction-Level Parallelism
• (Dynamic Scheduling Scoreboarding)

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What is a Scoreboard?

• A Scoreboard is a table maintained by the
  hardware
• keeps track of instructions being fetched,
  issued, executed etc.
• keeps track of the resources (functional units
  and operands) they use/need
• keeps track of which instructions modify which
  registers
• uses this information to dynamically schedule
  instructions
• very similar to a pen and paper calculation
• simple step-by-step procedure easily implemented
  in hardware

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MIPS with a Scoreboard
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Dynamic Scheduling with a Scoreboard

• Original development in CDC 6600
• Simplified example in HP3 for MIPS FP operations
  (Read Section A.8)
• Using neither renaming nor forwarding
• Values always move from registers to function
  units, and from function units back to registers
• However, write-back of results happen as soon as
  possible, not in a statically scheduled slot
• Out-of-order completion can give rise to WAR and
  WAW hazards
• Remember machine knows original program order
  (needed for hazard detection)
• Machine model
• 2 FP multipliers (10 cycles), 1 FP adder (2
  cycles), 1 FP divider (40 cycles)
• 1 integer unit for everything else (incl. memory
  references)

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Scoreboard Implications

• Out-of-order completion ? WAW, WAR hazards?
• for WAW stall in Issue until previous write
  completes
• for WAR stall in Write Result until previous
  read completes
• Need to have multiple instructions in execution
  phase
• ? multiple execution units or pipelined execution
  units
• Scoreboard keeps track of dependences, state of
  operations
• Scoreboard replaces ID, EX, WB with 4 stages

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Four Stages of Scoreboard Control

• Issue decode instr. check for structural
  hazards (ID1)
• If functional unit is free and no WAW hazard with
  other active instruction
• scoreboard issues the instruction to the
  functional unit and updates its internal data
  structure.
• If a structural or WAW hazard exists
• instruction issue stalls
• unless there is buffering between fetch and
  issue, no further instructions issue until these
  hazards are cleared.
• Read operands wait until no data hazards, then
  read (ID2)
• A source operand is available if no earlier
  issued active instruction is going to write it.
• When all source operands are available
• scoreboard tells the functional unit to proceed
  to read the operands from registers and begin
  execution.
• Thus, scoreboard resolves RAW hazards dynamically
  in this step
• instructions may be sent into execution out of
  order

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Four Stages of Scoreboard Control (cont.)

• Execution operate on operands
• The functional unit begins execution upon
  receiving operands
• When result is ready, it notifies the scoreboard
• Write Result finish execution (WB)
• Once scoreboard is aware that functional unit has
  completed execution, scoreboard checks for WAR
  hazards.
• If no WAR hazard
• it writes results
• If WAR hazard
• it stalls the completing instruction
• Example
• DIV.D F0,F2,F4
• ADD.D F10,F0,F8
• SUB.D F8,F8,F14
• CDC 6600 scoreboard would stall SUB.D until ADD.D
  reads ops

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Three Parts of the Scoreboard

• Instruction status Which of 4 steps instruction
  is in
• Functional unit (FU) status Indicates state of
  FU
• Nine fields for each functional unit
• Busy Indicates whether the unit is busy or not
• Op Operation to perform in the unit (e.g., or
  -)
• Fi Destination register
• Fj, Fk Source registers
• Qj, Qk Functional units producing source
  registers Fj, Fk
• Rj, Rk Flags indicating when Fj, Fk are ready
• Register result status Indicates which
  functional unit will write each register, if any
• blank when no pending instructions will write
  that register

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Scoreboard Example Cycle 0
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Scoreboard Example Cycle 1
First LD issues
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Scoreboard Example Cycle 2
Structural hazard on Integer unit second LD
stalls in IF stage
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Scoreboard Example Cycle 3
Second LD is still stalled
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Scoreboard Example Cycle 4
Second LD still stalled first LD done
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Scoreboard Example Cycle 5
Second LD issues as the structural hazard on
Integer unit has cleared
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Scoreboard Example Cycle 6
MULT issues
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Scoreboard Example Cycle 7
SUBD issues MULT stalled on LD
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Scoreboard Example Cycle 8a
DIVD issues SUBD stalled on LD
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Scoreboard Example Cycle 8b
LD writes F2 MULT and SUBD enabled
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Scoreboard Example Cycle 9
MULT and SUBD read operands and enter execution
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Scoreboard Example Cycle 10
Structural hazard on Add unit stalls the final
ADDD
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Scoreboard Example Cycle 11
SUBD and MULT are still in execution
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Scoreboard Example Cycle 12
SUBD writes results Add unit free structural
hazard resolves
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Scoreboard Example Cycle 13
Note WAR hazard between DIVD and ADDD
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Scoreboard Example Cycle 14
MULT still executing DIVD stalled on F0 (RAW
hazard)
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Scoreboard Example Cycle 15
MULT still executing
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Scoreboard Example Cycle 16
ADDD completes execution, ready to write result
into F6
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Scoreboard Example Cycle 17
WAR hazard ADDD stalls in Write Result stage
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Scoreboard Example Cycle 18
DIVD stalled (RAW hazard on F0), ADDD stalled
(WAR hazard on F6)
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Scoreboard Example Cycle 19
MULT completes execution
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Scoreboard Example Cycle 20
MULT writes result DIVD can proceed to read
operands at next cycle
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Scoreboard Example Cycle 21
DIVD reads operands WAR hazard on F6 is resolved
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Scoreboard Example Cycle 22
40 cycle Divide!
ADDD completes writing of result
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Scoreboard Example Cycle 61
DIVD completes execution ready to write result
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Scoreboard Summary

• CDC designers measured performance improvement of
  1.7 for compiled FORTRAN code, 2.5 for assembly
• No pipeline scheduling in software
• Slow memory (no cache)
• Limitations of 6600 scoreboard
• No forwarding
• Limited to instructions in basic block (small
  issue window)
• Number of functional units (structural hazards)
• Wait for WAR hazards
• Prevent WAW hazards