ECE 545 Project 1 Introduction

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ECE 545 Project 1Introduction Specification
Part I
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Cipher
Message / Ciphertext
m bits
Cryptographic Key
Encrypt/Decrypt
k bits
1 bit
m bits
Ciphertext / Message
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Secret-Key Ciphers
key of Alice and Bob - KAB
key of Alice and Bob - KAB
Network
Decryption
Encryption
Bob
Alice
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Block vs. stream ciphers
M1, M2, , Mn
m1, m2, , mn
memory
Block cipher
K
K
Stream cipher
C1, C2, , Cn
c1, c2, , cn
CifK(Mi)
Ci fK(mi, mi-1, , m2, m1)
Every block of ciphertext is a function of only
one corresponding block of plaintext
Every block of ciphertext is a function of the
current and all proceeding blocks of plaintext
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Typical Flow Diagram of a Secret-Key Block Cipher
Round Key0
Initial transformation
i1
Round Keyi
Cipher Round
ii1
r times
i lt r
Round Keyrounds1
Final transformation
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Basic iterative architecture
multiplexer
register
combinational logic
round key
one round
Encrypt/Decrypt
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Basic architecture Timing
CLK
M3
M1
M2
IN
C1
C2
OUT
r clock_period
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RC5
Ron Rivest, MIT, 1994
(Rons Code 5, Rivests Cipher 5)

• simple description

• variable key length - k

• variable i/o block size - m

• variable number of rounds - r

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RC5
One of the fastest ciphers
Basic operation
X times
Rotation by a variable number of bits
YltltX
Y
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RC5 w/r/b
w - word size in bits
w 16, 32, 64
input/output block size, m 2 words 2?w bits
Typical values w32 ? 64-bit
input/output block w64 ?
128-bit input/output block
b - key size in bytes
0 ? b ? 255
key size in bits, k 8?b bits
r - number of rounds
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Most commonly used sets of parameters
RC5 32/12/16
64 bit block 12 rounds 128 bit key
RC5 64/20/32
128 bit block 20 rounds 256 bit key
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RC5
Decryption
Encryption
A B C for i r downto 1 do B
((B?S2i1) gtgtgt A) ? A A ((A ? S2i)gtgtgtB) ?
B B B ? S1 A A ? S0 M A B
A B M A A S0 B B S1 for i 1
to r do A (A?B) ltltlt B S2i B (B?A)
ltltlt A S2i1 C A B
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Notation

• - concatenation
• - XOR
• X ltltlt Y - X rotated by Y positions
• - addition without carry (addition modulo
  2w)
• Si value of a round key i

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Variable Rotation
Software
Hardware
Mux-based rotation
C
Altltlt0
Altltlt16
C (A ltlt B) (A gtgt (32-B))
B4
B3
B2
B1
A ltltlt B
B0
32
ASM
AltltltB
variable rotation ROL32
High-speed clock
ROL A, B
A
fast clock CLK
min (B, 32-B) CLK cycles
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RC5 - Key Scheduling
k bits of the main key
2? r 2 round keys (2 ? r 2 ) ? w bits
Two magic constants
e - base of natural logarithms e 2.7182...
Pw Odd ((e-2) ? 2w)
Qw Odd ((?-1) ? 2w)
y
x-y
x
x
y
? - golden ratio

1.6180...
y
x-y
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RC5 - Key Scheduling
Initialize
S0 Pw for i0 to t-1 do Si Si Qw
t 2 ? r 2
Mix
i j 0 A B 0 do 3 ? maxt, c times
A Si (Si A B) ltltlt 3 B
Lj (Lj A B) ltltlt (AB) i
(i1) mod t j (j1) mod c
8?b
c
w
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Implementation of a secret-key cipher Round keys
precomputed
control
key
input
input interface
Control unit
key scheduling
encryption/decryption
memory of round keys
output interface
output
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clock
Encryption/decryption unit
reset
encrypt/decrypt
data output
m
n
data input
write
data available
full
data read
round number
round key(s)
Key memory
round key(s)
cycle number
k
key input
Key scheduling unit
key available
key read
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Project 1 - Organization

• 25 points total
• 4 phases, 1 phase per week
• grading
• 5 points for each phase 5 point
  for a final report
• individual project the same for all students
• contest for the best results (bonus points
• awarded to winners)

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Project 1 Honor Code Rules

• All students are expected to write and debug
  their codes individually
• Students are encouraged to help and support each
  other in all problems related to the- operation
  of the CAD tools,- basic understanding of the
  problem.

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Project 1 Optimization Criteria

• Maximum ratio
• Encryption/Decryption Throughput
• divided by
• Total Circuit Area

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Primary parameters of hardware implementations for
secret-key block ciphers
Latency
Throughput
Mi2
Mi
Mi1
Mi
Time to encrypt/decrypt a single block of data
Encryption/ decryption
Encryption/ decryption
Number of bits encrypted/decrypted in a unit of
time
Ci2
Ci
Ci1
Ci
Block_size Number_of_blocks_processed_simultaneo
usly
Throughput
Latency
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Project 1 - Organization

• Electronic submission by Monday, noon
• Feedback provided to students in class and during
  office hours

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Project 1 Platform tools

• Target devices Xilinx FPGA Spartan 2 family
• Tools
• VHDL Simulation Aldec Active HDL or ModelSim
• VHDL Synthesis Synplify Pro
• Implementation Xilinx ISE

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Phase 1, due Monday October 4, noon

• Draw a block diagram of a single round of
  encryption
• Draw a block diagram of a single round of
  decryption
• Draw a combined block diagram of a circuit
  capable of
• implementing a single round of both
  encryption and decryption with possible resource
  sharing
• Describe in VHDL combinational logic implementing
  one round of encryption and decryption using
  dataflow design style, i.e., using only
  concurrent statements
• 5. Write a testbench capable of verifying
  function of
• your circuit
• 6. Describe the entire datapath of the
  encryption/decryption
• unit in VHDL, assuming the use of the basic
  iterative architecture