BTeV Level1 Vertex Trigger

1
BTeV Level-1 Vertex Trigger

• Vertex 2001, September 23-28
• Michael Wang, Fermilab
• (c/o Gabriele Chiodini)

2
BTeV detector
3
BTeV trigger block diagram
4
L1 vertex trigger block diagram
5
L1 vertex trigger algorithm
FPGA Segment Finder (Pattern Recognition)

• Find beginning and ending segments of tracks from
  hit clusters in 3 adjacent stations (triplets)
• beginning segments required to originate from
  beam region
• ending segments required to project out of pixel
  detector volume

DSP Tracking and Vertexing

• Match beginning and ending segments found by FPGA
  segment finder to form complete tracks
• Reconstruct primary interaction vertices using
  complete tracks
• Find tracks that are detached from
  reconstructed primaries

6
L1 vertex trigger algorithm
Execute Trigger
7
L1 trigger efficiencies
8
L1 vertex trigger work-in-progress

• Status of L1 track finding vertexing code
• C version of full tracking vertexing code
  running on TI TMS320C6711 DSK board with TI Code
  Composer Studio v2.0.
• Goal is to avoid hand optimized assembly for the
  TI DSP in order to simplify code maintenance and
  achieve greater portability.
• Incorporating various optimizations in C use of
  intrinsics, in-line code vs. external function
  calls, single precision arithmetic, etc.
• Learning about behavior of TI CCS compiler in
  order to write C code that makes optimal use of
  all execution units in TI DSP.
• Immediate goal achieve estimated code execution
  times stated in BTeV proposal.

9
L1 vertex trigger work-in-progress

• Status of L1 track finding vertexing hardware
• Currently developing DSP prototype board with
  following features
• Room for up to 4 DSPs on mezzanine cards that
  will allow tests and comparisons of various types
  of DSPs (e.g. TI C67x family and latest TI C64x
  family)
• Input and output buffers implemented in FPGA with
  LVDS interface to Fermi-designed PCI test
  adapter. Buffer manager in FPGA will channel
  data to and from each DSP through DMA transfers.
• Trigger decisions from each processor sent
  through FPGA interface to on-board embedded
  processor that will format results and forward
  them to Global Level-1 through ArcNet interface
• Host computer serving as PTSM (Pixel Trigger
  Supervisor Monitor) connected to second on-board
  embedded processor through ArcNet. For processing
  messages/commands, DSP initialization, hardware
  monitoring and fault detection.
• JTAG ports for real-time debugging and initial
  startup of prototype.

10
L1 trigger 4-DSP prototype board
11
L1 vertex trigger work-in-progress

• Status of L1 track finding vertexing hardware
  (continued)
• Goals of the prototype board include the
  following
• Develop and test DSP kernel code.
• Develop and test Pixel Trigger Supervisor and
  Monitor (PTSM).
• Develop and test protocols for segment data, PTSM
  control messages, and trigger decisions sent to
  Global Level-1.
• Understand available and achievable network
  bandwidth between PTSM and DSP's.
• Test flow of input data to and output data from
  the DSPs.
• Run and benchmark L1 trigger tracking vertexing
  algorithm.

• Status of L1 segment finding algorithm
  hardware
• Segment finding algorithm currently being
  implemented in FPGA's.
• Simulations and queueing studies of algorithm
  concurrently being done using MATLAB.

12
Fault tolerant trigger DAQ system

• Final note
• The L1 vertex trigger is a major component in the
  larger framework of the BTeV trigger and DAQ
  system.
• This larger framework is a massive and complex
  real-time system involving thousands of FPGAs,
  DSPs, and PCs analyzing detector data generated
  at 1.5 Terabytes/s.
• BTeV hopes to benefit from an NSF grant to
  develop a semi-autonomous, self-monitoring,
  fault-tolerant / adaptive system for this
  purpose.
• Project will involve collaboration of computer
  scientists and physicists from Vanderbilt,
  Illinois, Syracuse, Pittsburgh, and Fermilab
  known as the Real Time Embedded Systems (RTES)
  Research Group.