The%20BTeV%20Level%201%20Muon%20Trigger%20Update - PowerPoint PPT Presentation

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The%20BTeV%20Level%201%20Muon%20Trigger%20Update

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octant-arm specific. 16-fold symmetry in hardware. no inter-octant communications. Algorithm Notes (continued) combinatoric explosion - suppressed ... – PowerPoint PPT presentation

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Title: The%20BTeV%20Level%201%20Muon%20Trigger%20Update


1
The BTeV Level 1Muon Trigger Update
  • Michael J. Haney
  • 27 January 2001
  • www.hep.uiuc.edu/engin/btev/reports/27jan01.ppt
    (and .pdf)

2
Algorithm
  • compress adjacent tube hitsand AND/OR
    (selectable) RR views
  • working radially inward,form valid RR2-U2
    pairs(fixed table size gt outer bias)
  • look-up V2s from RRU2sform RRUV2s
  • and RRV2s and UV2s, etc.as space/time
    permits...

U
2
V
2
3
3
4
4
6
8
R
10
3
Algorithm (continued)
  • window-search RR3sbased on RRUV2s
  • look-up U3s and V3sfrom RRUV2RR3s
  • look-up RR1s, U1s, V1sfrom RRUV2RRUV3s
  • declare RRUV1RRUV2RRUV3s(and various lessers)
    as tracks
  • calculate c2s (?)

4
Algorithm Notes
  • radially-inward processing
  • biased in favor of higher PT
  • implications on front end readout (order)
  • fixed table sizes
  • accommodates wall of fire near beam pipe
  • octant-arm specific
  • 16-fold symmetry in hardware
  • no inter-octant communications

5
Algorithm Notes (continued)
  • combinatoric explosion - suppressed
  • RRU2s require O(N2)
  • look-up steps require O(M)
  • window search? O(M) to O(M2)
  • could be fully implemented inthe Pixel Trigger
    DSP Farm
  • but compression/table-building may be donein
    (Pixel Trigger?) FPGAs

6
Status
  • Fortran code to analyze efficiency
  • work-in-progress
  • DSP code implementation
  • next
  • FPGA implementation (table building)
  • next
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