CMOS Noise Modeling and Measurements at 60 GHz

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CMOS Noise Modeling and Measurements at 60 GHz

• Chinh H. Doan
• Timo Karttaavi
• Robert W. Brodersen
• January 13, 2005

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Outline

• Review of millimeter-wave noise models
• Physics-based compact models
• Measurement-based empirical models
• Small-signal equivalent-circuit models
• Millimeter-wave noise measurements
• Noise parameter (variable ZS)
• Lossy pad de-embedding
• Simulated and measured results
• Individual CMOS transistors
• 60-GHz amplifier circuit

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RF Noise Model (van der Ziel)

• Short-channel drain current noise
• Induced gate noise
• Partial correlation due to NQS
• Flicker noise negligible at RF

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Compact Noise Models
BSIM4
Philips MOS Model 11

• Holistic noise model for short-channel and
  velocity saturation effects
• Noise partitioning for correlated gate noise

• Channel segmentation
• Automatically includes induced gate noise,
  partial correlation, NQS resistance

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Measurement-Based Noise Models

• Fixed bias point and frequency
• Two external correlated noise sources
• Two-port modeled as noiseless
• Represented with four real parameters (Fmin,
  Zopt, Rn)

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Equivalent-Circuit Noise Models
PRC
Pospieszalski

• Uncorrelated gate noise voltage and drain noise
  current
• NQS resistance contributes thermal noise at
  ambient temperature
• One independent variable

• Essentially equivalent to van der Ziel model
• Extract P, R, C from measurements

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Extended Transistor Noise Modeling
Pospieszalski noise model used for intrinsic
device

• Lumped, frequency-independent parasitic model
• RG and rnqs thermal noise for gate resistance and
  induced gate noise (not correlated to drain
  noise)
• Excess short-channel drain noise current (gamma
  1.4)

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50-75 GHz Noise Parameters (VTT)

• 50-75 GHz noise parameter characterization (Fmin,
  Zopt, Rn)
• VTT measuring noise parameters for BWRC 130-nm
  CMOS devices (individual transistors, cascodes,
  etc.)

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Test Structures and Pad De-embedding
80x1/0.13 NMOS

• Test structures
• Calibration structures (Open, short, through)
• NMOS 40x1, 60x1, 80x1, 100x1, 80x1_Ldeg, Cascode
  80x1
• Bias settings (IDS/W 50, 100, 150, 200, 250
  uA/um)
• Pad de-embedding Hillbrand76
• Pads are passive, reciprocal network
• Noise correlation matrices
• De-embed cascaded noisy two-ports

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40x1 Noise Params (IDS100uA/um)
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40x1 Noise Params (IDS 150uA/um)
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60x1 Noise Params (IDS 100uA/um)
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60x1 Noise Params (IDS 150uA/um)
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80x1 Noise Params (IDS 100uA/um)
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80x1 Noise Params (IDS 150uA/um)
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80x1 Noise Params (IDS 200uA/um)
Fitting not as good
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80x1 Cascode Noise Params (IDS 150uA/um)
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60-GHz Amplifier Schematic

• 3-stage cascode amplifier design
• Cascode transistors improve isolation, stability
• Input/output matching networks designed to match
  50 O
• Pads are included as part of amplifier
• Designed using only measured components

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50-75 GHz Noise Figure (Agilent)
Agilent 8973A Noise Figure Analyzer
V-band Noise Source
Isolator
Waveguide Probes
OML Mixer
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60-GHz Amplifier Noise Figure
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Conclusions

• Pospieszalski intrinsic noise model
• Increased channel current noise (gamma 1.4)
• RG and rnqs for gate resistance and induced gate
  noise (uncorrelated to drain noise)
• VTT noise parameter device characterization
• Accurate prediction of Zopt
• Fmin within about 0.5 dB
• Agilent circuit NF characterization of 60-GHz
  amplifier
• Models provide good circuit NF prediction
• Remaining issues
• Phase error in Zopt Probe placement? Correlated
  noise? More sophistacated noise model?
• Comparison to compact models?

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Acknowledgments

• VTT Millilab
• H. Tran and K. Fujii, Agilent Technologies
• DARPA TEAM project
• STMicroelectronics