Review 2

1
Review 2

• Lecture 16

2
Midterm

• 10/11 (Friday)
• One hour
• Chapters 1-7 and 11, as well as appendices A-H
• Closed book and notes
• A summary of key Verilog features provided

3
Exam Problem 1
primitive FF (q, clock, rst_, set, data) input
clock, rst_, set, data output q, reg q
table // clk rst_ set data state q 0
? 0 // reset 1 1 ? 1 //
set r 1 0 0 ? 0 // load 0 r 1 0 0
? 1 // load 1 f 1 0 ? - //
falling clock ? 1 0 ? - // steady
clock r 1 0 1 1 1 r 1 0 0 0 0
endtable endprimitive
4
Exam Problem 2
module WRONG_FF (q, q_, clock, rst_, set, data)
input clock, rst_, set, data output q, q_
reg q assign q_ q always _at_(posedge
clock or rst_ or set) begin if (rst_0)
q0 else if (set1) q1 else q
data endmodule
5
Exam Problem 2
module FF (q, q_, clock, rst_, set, data)
input clock, rst_, set, data output q, q_ reg
q assign q_ q always _at_(rst_ or set)
begin if (rst_0) q0 else if (set1)
q1 end awlays _at_(posedge clock) if
((rst_1) (set0)) q data endmodule
6
Problem 3a
Vcc
module nand2(y, a, b) output y input a,
b supply1 PWR pulldown(y) pmos(y,
PWR, a) pmos(y, PWR, b) endmodule
a
b
y
7
Problem 3b
result_1 Pu1 to St1 result_2 Pu0 to We0
result Pu0 to St1
8
Exam Problem 5
initial begin 1 sig_c 1 0 1 sig_a
1 sig_b lt 2 sig_a sig_c lt (_at_ posedge
sig_b) sig_b 1 sig_a 0 fork 1 sig_a
1 2 sig_b 0 sig_c sig_a join end
time 1 2 3 4 5 6 7 sig_a x x x 1 0 1 1 sig_b
x x x x x 1 0 sig_c x x 0 0 0 0 0
9
Problem 4
and (3, 4) (w1, a, b) nor (5, 2) (y, w1, c)
(a gt y) (9, 5) (b gt y) (9, 5) (c gt y)
(5, 2)
10
Problem 2.3
Write structural description with primitive gates
for the Boolean equation y1 (a0)b2
(a2)a0b2 a0((b1))b0 module P23(y1, a0,
a2, b0, b1, b2) input a0, a2, b0, b1, b2
output y1 not(not_a0, a0) and(t1, not_a0,
b2) not(not_a2, a2) and(t2, not_a2, a0, b2)
not(not_b1, b1) and(t3, a0, not_b1, b0) or(y1,
t1, t2, t3) endmodule
11
Problem 2.4
Write structural description with continuous
assignment for the Boolean equation y1
(a0)b2 (a2)a0b2 a0((b1))b0 module
P23(y1, a0, a2, b0, b1, b2) input a0, a2, b0,
b1, b2 output y1 assign y1 (a0)b2
(a2)a0b2 (b1)b0 endmodule
12
Problem 2.11
Using Verilog predefined primitive, write a
description of the circuit below module p211(q,
qb, set, rst) input 70 set, rst output
70 q, qb nor 70 (q, rst, qb) //
tested, works fine nor 70 (qb, set, q) //
tested works fine endmodule
13
Problem 2.12
Using continous assignment, write a description
of the circuit below module p212(q, qb, set,
rst) input 70 set, rst output 70 q,
qb assign q(rst qb) assign qb (set
q) endmodule
14
Problem 2.21

• Which of the following assignments have correct
  syntax? What is stored in the memory?
• A8b101 0000 0101
• B5o9 wrong
• C12HAA 0000 1010 1010
• D4BBB wrong
• E4dx3, or E4dx3 wrong
• F4hz zzzz
• G4O8 wrong
• H8hz9 wrong