Single Event Upsets in preFPIX2Tb

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Single Event Upsets in preFPIX2Tb

• Talk given by Gabriele Chiodini (updated)
• Fermilab April 21, 2001 BTeV meeting group

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Summary

• What a Single Event Upset (SEU) means
• DACs and shift registers in preFPIX2Tb
• Experimental Setup in Indiana University
  Cyclotron Facility (IUCF)
• Beam profile and fluence measurements
• Results
• SEU rate measurement
• DACs response before and after irradiation
• Estimated error in BTeV
• Conclusions
• Next

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What a Single Event Upset (SEU) means (1)

• The SEU is a non destructive phenomenon induced
  by radiation in electronics chips.
• SEU is caused by heavily ionizing fragments and
  recoils depositing enough charge in a sensitive
  node of an electronic device.
• SEU could change the logic state of a memory cell
  (Flip-Flop) and corrupts downloaded data stored
  on-chip registers.
• Depending on the SEU rate of a chip appropriate
  reset mechanisms could be needed in the design.

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What a Single Event Upset (SEU) means(2)

• Nerror total bit errors
• F Itime integrated fluence
• Nbits number of bits exposed
• sbit one bit SEU cross section

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DACs and S-Rs in preFPIX2Tb (1)

• PreFPIX2Tb is implemented in 0.25um CMOS
  technology following rad-hardening design rules
• PreFPIX2Tb pixel readout chip has
• A pixel array of 32 rows x 18 cols 576 pixels
• A kill and an injection shift-register, both 576
  bit long and distributed along the array
• 14 DACs 8 bit long positioned on the periphery
  to set voltages and currents level for the
  front-end cells
• PreFPIX2TB contains complete End Of Column
  Logic and Time Stamp Counter

Chip size
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DACs and S-Rs in preFPIX2Tb (2)
BCO_clock
Shift_control
Shift_in
5bit
5bit
3bit
nbit
Chip_id
Reg
Cmd
W/Data (if any)
Shift_out
nbit
R/Data (if any)
Robust absolute addressing (no daisy chain)
BCO_clock
Shift_control
Shift_in

• The ChipId is wire bonded (not upsetable)
• The DACs can be read back and downloaded in a
  non destructive way without interfering with the
  readout

Shift_out
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Experimental Setup in IUCF(1)
Concrete walls
203 MeV p
Chip 1 Chip2
LVDS driver-receiver card
Frame support
Exp. Crate PCI card
LVDS driver-receiver card
Power supplies
Lap top Ccode
100 feet
18 feet
GPIB
Terrifying starts a Tektronix PS provided 27 V
instead of 2.5 V and we lost a board
Control room
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Experimental setup in IUCF

• The experimental procedure consisted in
• Download a know data pattern in the shift
  registers and DACs.
• DACs programmed to the default value.
• Shift-registers programmed to have half pixels
  killed and half injected according to a random
  pattern.
• Wait one minute and read back the shift registers
  and DACs to check for errors.
• Data errors reported on screen and saved in a
  file.
• Loop on steps 1, 2 and 3.

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203 MeV proton beam relative beam profile
The relative beam profile has been measured
scanning by a photometer a film exposed to the
proton beam.
7.2 mm chip side
Averaged over
Roughly less than 10 uncertainty in the total
fluence due to the board position uncertainty
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203 MeV proton beam some more detail

• Beam centered on the chip by a laser spot.
• Video camera displaying the board to check for
  eventual movement during the test.
• Absolute fluence measured by a Faradays cup.
• A second electron emission monitor (15 copper
  foils SEEM) measured the instantaneous fluence.
  

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Results run table
Run Time s Fluence s-1cm-2 Integrated fluence cm-2 Bit errors Bit errors in s-r Bit errors in DAC
0 10800 0 No beam 0 0 0
1 687 2.9E9 2E12 0 0 0
2 804 1.2E10 1E13 2 211 0
3 781 1.3E10 1E13 3 321 0
4 3632 1.3E10 4.8E13 11 853 330
5 5730 4.0E9 2.3E13 9 725 211
6 10501 1.3E10 1.4E14 38 33825 541
7 32400 0 nobeam 0 0 0
Total 2.33E14 14Mrad(Si) 63 531835 1082
transition from 0 to 1 transition from 1 to 0
N.B. The SRs were downloaded with equal number
of 0s and 1s but the DACs with 82 0s and 30
1s.
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Results bit error rates

• We observed 63 bit errors in 22135 seconds
  during the exposure, this gives an average bit
  error rate of 2.8E-3s-1.
• We observed no bit errors in 43200 seconds with
  no exposure, this gives an upper limit of the
  accidental bit error rate of 2.3E-5s-1.

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Results SEU cross sections shift-register
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Results SEU cross sections DAC
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Results SEU cross sections
N.B. the uncertainty in the integrated fluence is
less than 10
Comparable to what reported by other
collaborations
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Results DACs response before and after
Irradiation
14 Mrad(Si) 203 MeV proton beam
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Estimated error rate in BTeV
F is the number of tracks crossing plane 30
according to Geant at L2E32cm-2s-1 as evaluated
by Dave from Pennys file. I assumed the covered
area is 10cm by 10cm and a beam gap BG temporal
structure of 99/1590.62.
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Pixel detector fluence from Mars(1)
Extracted from A.Uzunian, BTeV meeting, 1-27-01.
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Pixel detector fluence from Mars(2)
Radiuscm ltCh. Hadronsgt (Egt10MeV)Hz/cm2 ltNeutronsgt(Egt14MeV)Hz/cm2 ltNeutronsgt(Elt14MeV) Hz/cm2 ltelecsgt and ltggt (Egt100KeV) Hz/cm2
0.6-2 6.4E6 7.2E5 2.5E5 1E6 and 6E6
2-3 2E6 3E5 1.8E5 4E5 and 2E6
3-4 9E5 1.7E5 1.5E5 2.3E5 and 1E6
4-5 5E5 9.4E4 1.3E5 1.5E5 and 6E5
5-6 3E5 7E4 1.2E5 9E4 and 4.8E5
6-7 2E5 5E4 1E5 7E4 and 4.9E5
average 1.E6 (3.7E9h-1) - - -
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Conclusions

• We observed evidence of SEUs in preFPIX2Tb with
  a rate similar to what reported from other
  collaborations.
• The response of one DAC after 14Mrad(Si) of
  203MeV proton irradiation has relative small
  (about 20mV) voltage shift in the output.

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Next

• Understand carefully the implication of the
  measured SEU rate on the chip design
• Measure all DACs response after irradiation when
  the board is back from Bloomington.
• We intend to do further SEUs tests in June with
  sensors bump bonded to preFPIX2Tb.