Pontifcia Universidade Catlica do Rio Grande do Sul

1
Pontifícia Universidade Católica do Rio Grande do
Sul

• Parallel Decoding Cyclic Burst Error Correcting
  Codes

Gabriel Marchesan Almeida Subject Digital
Systems Testing
October/2005
2
Parallel Decoding Cyclic Burst Error Correcting
Codes

• ECC Codes - Linear Feedback Shift Register (LFSR)
  
• sequential logic
• less hardware
• do not support high-speed data transfers

(N, K) (7,4) Ex (1000000), (0101001),
(0110100), (0001111) are valid 7-bit error
patterns representing 3-bit burst errors.
Ex (0000111), (0000100), (0000110)
are not valid 7-bit burst errors.
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• ECC Codes - Linear Feedback Shift Register (LFSR)

• Sequential decoders with linear feedback shift
  registers use polynomial algebra to determine
  burst error pattern and locate where the burst
  starts.
• Consider as an example the (7,3)
  double-symbol-error correcting RS code. We
  describe the generator polynomial in terms of its
  2RN-K 4 roots, as follows

g(X ) a3 a1X a0 X2 a3 X3 X4
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Encoding in Systematic Form
• Message to be transmitted
• We first multiply the message polynomial a1 a3X
  a5X2 by Xn-k X4, yielding a1X4 a3X5 a5X6
• We next divide this message polynomial by the
  generator polynomial, a3 a1X a0X2 a3X3
  X4, this polynomial division results in the
  following remainder (parity) polynomial

p(X) a0 a2X a4X2 a6X3

• Then, the codeword polynomial can be written as
  follows

U(X) a0 a2X a4X2 a6X3 a1X4 a3X5
a5X6 (100)(001)X(011)X2(101)X3(010
)X4(110)X5(111)X6
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Encoding in Systematic Form

a0
a4
a5
a2
0
a4
a1
a6
a1
a2
a3
a6
a2
a0
a1
a3
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Decoding

R(X) a0 a2X a4X2 a0X3 a6X4 a3X5
a5X6 (100)(001)X(011)X2(100)X3(101
)X4(110)X5(111)X6
e(x) 0 0X 0X2 a2X3 a5X4 0X5 0X6

• The syndrome is the result of a parity check
  performed on r to determine whether r is a valid
  member of the codeword set. If in fact r is a
  member, the syndrome S has value 0. Any nonzero
  value of S indicates the presence of errors.
• S1 r(a) a0 a3 a6 a3 a10
  a8 a11
• a0 a3 a6 a3 a3 a1
  a4
• a1
  a4 a0 a4
• 
  a2 a5
• 
  a3
• S2 r(a2) a0 a4 a8 a6 a14
  a13 a17
• a0 a4 a1 a6 a0 a6
  a3
• a5
• S3 r(a3) a0 a5 a10 a9 a18
  a18 a23
• a0 a5 a3 a2 a4
  a4 a2
• a6
• S4 r(a4) a0 a6 a12 a12 a22
  a23 a29
• a0 a6 a5 a5 a1
  a2 a1

ERROR
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Error Location

For the (7,3) double-symbol-error correcting RS
code, the matriz size is 2 x 2, and the model is
written as follows
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Error Location

To solve for the coefficients ?1 e ?2 and of the
error-locator polynomial, ?(x), we first take the
inverse of the matrix A. The inverse of a
matrix A is found as follows
Therefore,
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Error Location

We begin our search for the error locations by
solving for the coefficients of the error-locator
polynomial, ?(x)
Once these roots are located, the error locations
will be known. In general, the roots of ?(x) may
be one or more of the elements of the field. We
determine these roots by exhaustive testing of
the ?(x) polynomial with each of the field
elements, as show below. Any element X that
yields ?(x) 0 is a root, and allows us to
locate na error.
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Error Values

Now, we solve Equation for the error values, as
follows
The demonstrated algorithm repairs the received
polynomial, yielding and estimate of the
transmitted codeword, and ultimately delivers a
decoded message. That is
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Parallel Decoding

• We will divide the received word into a number
  of overlapping R-bit frames where each frame
  overlaps with its adjacent frames by exactly l-1
  bits.
• Notice that the zeroth frame starts at the
  zeroth bit of the received word. The jth frame
  starts at the j(R-l1)th bit and ends at the
  (j(R-l1)(R-1))th bit of the received word.
• The number of frames M in a received word with
  length N-bits is given by

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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Parallel Decoding

For a received word V, the decoder either outputs
a codeword V after l-bit burst error correction
or indicates if the received word is corrupted by
an uncorrectable error (UCE) pattern. Syndrome
Generator gerenates syndrome S by using parity
calculations on the received word. This syndrome
is fed to the syndrome decoder. Syndrome Decoder
- outputs na N-bit binary pattern E which is
either l-bit burst error pattern or an all-zero
pattern. Error Corrector performs V V ? E,
bitwise exclusive-OR of vectors V and E, to
obtain the corrected word. If S?0 and E0, the
Error Detector indicates that an uncorrectable
error has occurred.
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Parallel Decoding

The syndrome decoder has M error pattern
generators in parallel. These M error pattern
generators correspond to M frames of the received
word. Each error pattern generator performs some
parity calculations on the syndrome S and outputs
an R-bit binary vector which is either an
all-zero vectors or a vector representing an
l-bit burst error pattern. Using these R-bit
binary vectors, the error calculator determines
the N-bit error pattern E.
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Parallel Decoding Cyclic Burst Error Correcting
Codes

• Parallel Decoding

This Table shows the hardware complexity of the
parallel decoding circuit for the 4-bit burst
error correcting cod which was generated by
g(x)(1x11)(1xx4). The codes considered in
this table are shortened quasicyclick codes of
the original (165,150) code with information
length K equal to 32, 64 and 128 bits. In this
case, we count a 4-input AND/OR gate as one gate
and a 2-input XOR gate as 1.5 gates.