Gigabit SerDes for real-time applications

1
Gigabit SerDes for real-time applications

• Alberto Aloisio
• Università di Napoli Federico II
• and INFN
• Email aloisio_at_na.infn.it

2
Overview

• Typical architectures of Gigabit SerDes
• Real-time issues
• GLink chip-set
• GLink DWDM
• What is next DREAM and NEMO
• Conclusions

3
Texas TLK2501

• 75 to 125 MHz TX clock
• 16-bit word payload, full-duplex
• 1.5 to 2.5 Gbit/s
• Twisted pair or Fibre
• 2.5V supply, 3.3V tolerant I/O
• Low Power
• TX RX 500 mW (max)
• Pin-to-pin compatible with even faster devices,
  up to 3.125 Gbit/s
• But ...

4
TLK latency

• Trasmission latency is stable once the lock is
  achieved
• But it can change after a reset, a power cycle or
  a resynch following a loss-of-lock
• According to the data-sheet, the worst-case
  latency changes are
• _at_1.5Gbit/s 23.3 ns
• _at_2.0Gbit/s 17.5 ns
• _at_2.5Gbit/s 14.0 ns

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TLK Latency (simulation)

• Latency is constant within the same run
• Latency may change after a reset
• Data integrity is guaranteed, but critical
  signals will arrive at destination with different
  timing

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Texas SLK2501

• Multirate SONET transceiver, full duplex
• OC48/24/12/3
• 155 Mbit/s, 622 Mbit/s, 1.25 Gbit/s, 2.5 Gbit/s
• 4-bit word payload
• 622 MHz clock required for proper operations
• 2.5V supply, 3.3V tolerant I/O
• Power Consumption
• TX RX 900 mW (max)

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Cypress CYS25G0101

• OC48 SONET transceiver, full duplex
• 2.5 Gbit/s
• 16-bit word payload
• 155 MHz clock required for proper operations
• 3.3V supply
• Power Consumption
• TX RX 1 W (typ)

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SONET Latency

• Latency is not even mentioned in data-sheet
• Different clocking strategies affect the timing
• The FIFO in the TX makes it quite hard to predict
  the behavior

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FIFO Timing Empty boundary

• Due to clock skews, the FIFO can be seen empty
  even if data is already available
• This changes the trasmission latency

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SLK and CYS Latency (simulation)

• TX data is written synchronously with TX clock
  (not shown)
• TX clock vs. REF clock jitter is seen as latency
  jitter
• Even if TX clock is derived by REF clock (forward
  clocking), FIFO may introduce a1-clock cycle
  jitter

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Glink Features

• 13 MHz to 70 MHz clock
• 260-1400 Mbit/s
• 16-bit word payload
• Qualifiers to distinguish between data and
  controls
• Twisted pair or Fibre
• 3.3V supply, 5V tolerant I/O
• Power consumption
• TX 660 mW (max)
• RX 800 mW (max)
• Last generation of the HDMP-1000 family
• Fully synchronous link
• Low, fixed latency
• Phase-locked clocks

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Glink Clock Tree

• TX and RX clocks are independent (with no phase
  relationship) but with the same frequency (/-
  100ppm)

• TX and Recovered Clock are phase locked
• RX and Recovered clocks are not phase locked

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DREAM GLink Node

• A full-duplex node based on Glink has been
  designed and tested for the DREAM program
• Serial streams on coax cable to interface with
  different optical devices
• Infrared analysis to study thermal issues
• Test conditions
• Still air, Tamb 20C
• 40MHz clock, 800Mbit/s
• PRBS sequence

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DWDM board

• Agilent AFKC family DWDM transponder
• Eval board from Agilent
• Control and Monitoring SW on PC
• No-Disclosure Agreement signed with Agilent for
  the source code
• Infrared analysis to study thermal issues
• Test conditions
• Still air, Tamb 20C
• 40MHz clock, 800Mbit/s
• PRBS sequence

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DREAM Test Bench

• Glink node has been interfaced with the
  trasponder
• I/O logic levels are compatible
• no translators needed
• excellent signal integrity
• Loopback tests performed at 800Mbit/s
• No errors observed in 5-hour run

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Glink latency (lab test)
TX data
Fixed latency

• TX and Recovered clocks are phase-locked
• Latency is fixed
• 160ns with 10m fibre

RX data
TX clock
Recovered clock
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DREAM and NEMO

• A GLink-based DWDM node is presently under design
• This node will be a plug-in on a carrier FCM
  board (Bonori, Ameli) to be tested in the NEMO
  DAQ environment
• Plug-in DWDM node time schedule
• Final specs (form factor, connectors pin-out,
  ...) May 2005
• 2 prototypes June 2005

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Conclusions

• Glink allows designing a fully synchronous link
  with fixed latency
• Proof-of-concept of a DWDM node based on Glink is
  already available
• Plug-in mezzanine card (Napoli, DREAM) and
  FCM-carrier (Roma, NEMO) are presently under
  design
• Jitter tests with very long fibres (100 Km) are
  needed to fully characterize the link