Verification Plan

1
Verification Plan Levels of Verification

• The Verification Plan
• Yesterdays and todays design environment
• Design specification document
• Verification success
• Levels of verification

2
The Verification Plan

• Just as a design meets a specification, the
  verification plan is the specification for the
  verification effort.
• Defines
• What is success
• How a design is to be verified
• Functional correctness
• Which testbenches to write
• Schedule for verification effort

3
In The Past

• Verification was left to each designer to do as
  they wished
• Verification was done as time allowed
• Emphasis was does chip work?
• Have progressed from does chip work? to
• Does chip work in the system?
• Does chip work in the system as specified?
• Does the system work as specified?

4
Todays Environment

• Wish to have system integration go smoothly
• Simulate chip(s) in system environment to
  identify problems early, preferably during design
  and prior to fabrication
• Tools, if effectively used, can help
• Simulation
• Linting
• Other tools

5
Specifying the Verification

• When will verification of design be completed to
  the required degree of confidence
• Must determine
• How much work verification will require
• How many people are needed for the verification
  effort
• How long will the verification effort take

6
Design Specification Document

• Verification effort relies on a complete
  specification document
• Must be a written document
• Is the common source for both the designs
  implementation and its verification
• When designs output is not as expected this
  document helps determine whether the design is
  correct (verification in error) or not
  (verification correct)

7
The Plan 1st Time Success

• The verification plan defines what success is
• Insures all essential features of design are
  appropriately verified
• Documents which features are essential and which
  are optional
• Not all features of the final design need be
  included in defining 1st time success
• Final success requires that all features in the
  final design are working and verified so.

8
Levels of Verification

• As the level of focus changes, what is being
  verified changes also
• The level of granularity is also included in the
  plan
• Best partitions to verify are those where
  controlability and observability are best
• Partitions being verified must have relatively
  stable functionality and interfaces

9
Unit-Level Verification

• Design units are logical partitions and vary from
  small to large, simple to complex
• Small/Simple - FIFO, small state machine
• Large/Complex - PCI slave interface, DSP datapath
• Often have interfaces that are not fixed and firm
• Often functionality is not yet fixed and firm
• Any reasonable size project will have a large
  number of design units
• Verification of the entire design at this level
  would probably be too time consuming

10
Reusable Component Verification

• Component is designed to its own specification
• Component intended to be used as-is in many
  different designs
• Typically the component implements a common
  function or allows connection to a standardized
  interface
• Component is used in many designs - focus is on
  its functionality
• Potential users must have confidence that design
  is indeed correct

11
ASIC FPGA Verification

• These units form a physical and possibly a
  logical partition
• Often have their own specification
• Often contain a collection of independently
  designed and verified components
• Todays ASICs and FPGAs are too complex to verify
  and debug during integration. Need verification
  for them prior to synthesis or downloading the
  programming.

12
System-Level Verification

• There are many definitions for a system!!!
• In the book - a system is a logical partition
  composed of independently verified components.
• System could be
• composed of a few reusable components
• a subset of an SoC ASIC
• ASICs (or part of ASICs) on different boards
• Focuses on interaction between components
• Relies on individual components being
  functionally correct

13
Board-Level Verification

• Confirm that component connectivity is correct
• Some components on boards, such as capacitors, do
  not translate easily to digital domain
• Depending on the complexity level, could be used
  to verify functionality (as with any other level)
• Must make sure what is verified is what is
  manufactured (as with all levels)