ECS 154A Computer Architecture

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ECS 154AComputer Architecture
Fall 2003 UC Davis Instructor Koling Chang
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Outline

• Administrative
• Instructor, TA
• Resources
• Grading
• Topic of Study
• Syllabus
• Topic Overview

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Instructor and TA

• Instructor Koling Chang (kchang_at_cs.ucdavis.e
  du)
• Office Hour Monday 1105am-1200pm
• Office Kemper Hall, Room 2123
• TA Minh Huynh (huynh_at_cs.ucdavis.edu)
• Course Website http//wwwcsif.cs.ucdavis.edu/cs15
  4ab
• Prerequisite ECS 50 or EEC 70, and ECS 110

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Resources

• Textbook S.P. Dandamudi, Fundamentals of
  Computer Organization and Design
• Lab work software MaxPlus II

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Grading

• 4 lab-work assignments (6, 6, 10, 10)
  (interactive grading)
• 3 written homework assignments (18 total)
• Midterm (25)
• Final (25)
• Grading issues have to be raised within a week
• Final grading based on distribution
• A/A- (40)
• B//- (50)
• C/D/E/F (lt10)

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Topic of Study

• Digital Design
• Boolean Algebra, Gates, Combination and
  Sequential Logic
• ALU
• Interconnection
• Buses
• Memory
• Memory Systems, Memory Management, Cache, Virtual
  Memory
• I/O
• Memory mapped/Programmed I/O, DMA, Interrupts,
  Networks, Peripherals

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Syllabus

• 1.         Course Overview
• 2.           Digital Logic Basic building blocks
• 3.            Boolean, Logic Design Process ,
  Simplification
• 4.            Simplification2, Generalized Gates
  (hw1)
• 5.            Combination Circuits mux, demux,
  decoder, encoder
• 6.            Comparators, Fixed-point
  Arithmetic, Adder, ALU
• 7.            Multiplication and Division (lab1)
• 8.            Floating-Point Arithmetic, ALU,
• 9.            ROM, Programmable Devices
• 10.        Sequential Logic clock, latches
  (hw2)
• 11.  flip-flops, counters
• 12.        shift register, state machines
• 13.        Buses design issues, sync bus, async
  bus (lab2)
• 14.        bus arbitration,
• 15.        bus examples (hw3)
• 16.        Midterm review
• 17.        Midterm
• 18.        Memory memory system, memory block
  design
• 19.        larger memory, memory modules, memory
  mapping

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Course Overview

• Various aspects of computer architecture
• Users view (UI)
• Programmers view (OS/API/ISA)
• Implementers view (Arch./Funct. spec, low-level)
• Architects view (PRD, high-level)

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A Users View

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A Programmers View
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Architects View of a System
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Implementers View

• Observing design specification from architecture
  team
• Designing and implementing detail components to
  meet requirements

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CPU
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CPU Example

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ALU Example

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Memory

• Ordered sequence of bytes
• The sequence number is called the memory address
• Byte addressable memory
• Each byte has a unique address
• Memory address space
• Determined by the address bus width
• Memory size is limited by address space
• Pentium has a 32-bit address bus
• address space 4GB (232)

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Memory Unit

• Address
• Data
• Control signals
• Read
• Write

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Memory Mapping

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Buses

• System components are interconnected by buses
• Bus a bunch of parallel wires
• Uses several buses at various levels
• On-chip buses
• Buses to interconnect ALU and registers
• A, B, and C buses in our example
• Data and address buses to connect on-chip caches
• Internal buses
• PCI, AGP, PCMCIA
• External buses
• Serial, parallel, USB, IEEE 1394 (FireWire)

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System and Bus Example
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I/O

• I/O devices are interfaced via an I/O controller
• Takes care of low-level operations details
• Several ways of mapping I/O
• Memory-mapped I/O
• Reading and writing similar to memory read/write
• Uses same memory read and write signals
• Most processors use this I/O mapping
• Isolated I/O
• Separate I/O address space
• Separate I/O read and write signals are needed
• Pentium supports isolated I/O
• Also supports memory-mapped I/O

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I/O
Interrupts
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How Do We Build Them?

• Everything is logic.
• Logic is represented by voltages and operated by
  logic gates.
• Complex system is built from functional units,
  components, and devices.
• Lets continue with logic design next week.