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Seamless CVE

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Steps of Design Cycle. High-level system design: Define system requirements and partition. ... Perform the hardware portion of a simulation. ... – PowerPoint PPT presentation

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Title: Seamless CVE


1
Seamless CVE
  • Neena Nambiar
  • March 23rd 2004

2
Outline
  • Design Cycle
  • Components
  • Optimization
  • Memory Mapping
  • Miscellaneous

3
Steps of Design Cycle
  • High-level system design
  • Define system requirements and partition.
  • Detailed design and implementation
  • hardware and software follow different paths.
  • Physical integration
  • hardware prototype and software exist, load
    software onto hardware and test.

4
Design Cycle
5
Components of Seamless CVE
  • Instruction Set Simulators(ISS/ HCE)
  • Performs software portion of a cosimulation
    session.
  • Target software is compiled and linked to give
    machine code.
  • Executes machine code.
  • Cosimulation Kernel
  • Controls communication between hardware and
    software simulation.

6
Components (contd..)
  • H/W Simulator Interface H/W Simulation Kernel
  • Perform the hardware portion of a simulation.
  • One or more processor bus-interface models are
    instantiated along with optimizable memory.
  • Kernel executes the HDL simulation of the design.

7
ISS and HCE
  • ISS
  • Software application that models the functional
    behavior of a processors instruction set.
  • Eg. ISS and debugger combination is the XRAY ISS.
  • HCE
  • Compilers on the workstation can be used.
  • Executes directly on the workstation that runs
    software simulation.

8
Bus Interface Models
  • Supplies the input and output pin behavior.
  • Internal logic of processor is not taken care of
    by bus interface model.
  • Simulates the bus interaction performed by the
    processor in case of an event such as a fault or
    interrupt.

9
Advantages of Seamless
  • Optimizable Memory Models
  • Coherent Memory Server which can be accessed
    independently by both the software and the
    hardware simulation
  • Both hardware and software have identical view of
    the Coherent Memory.
  • Hardware simulation activity is suppressed

10
Seamless Memory Architecture
11
Optimizations
  • Data access optimization
  • Instruction Fetch optimization
  • Time Optimization

12
Data Access Optimization
  • Unoptimized
  • memory access processor bus-interface model
    read/write bus cycle(h/w sim).
  • Accelerates cosimulation by suppressing bus
    activity during memory accesses.
  • The ISS reads or writes directly to memory
    through the coherent memory server.

13
Instruction Fetch Optimization
  • It suppresses hardware bus activity during
    instruction-fetch cycles
  • For all instruction fetches taking place in
    regions of memory that are optimizable.

14
Time Optimization
  • Eliminates hardware clock cycles in addition to
    bus activity during optimized access. Methods
  • Off Hardware clock cycles not suppressed.
  • Full All hardware clock cycles eliminated
  • Ratio Ratio of hardware to software cycles is
    specified (useful for interrupt driven systems)

15
Memory Mapping
  • Defines the way in which software access to
    memory correlates with the hardware simulation.
  • Memory Instance mapping How Seamless memory
    instances map into the address space of a given
    processor.
  • Memory Access mapping How different ranges of
    memory may be accessed.

16
Memory Access
  • Access types hardware-only, illegal, software,
    Optimizable
  • Number of bus cycles and wait states required for
    read and write operations.
  • This is required so that the hardware can keep up
    with the software during optimized access.

17
Coherent Timer Interface
  • ISS is no longer synchronised with the hardware.
  • Problem !!
  • When software in ISS depends on the timing of
    device modeled in hardware.
  • Updates timer states when hardware cycles are
    suspended.
  • Uses number of processor clock cycles.

18
C-Bridge model
  • An interface that allows hardware designs
    expressed in high-level languages, based on C
    language to participate in cosimulation with
    Seamless CVE.
  • Like SystemC, these languages may be augmented
    with libraries,
  • They are compiled and debugged with C or C
    tools.

19
Co-Applications
  • Altia
  • Application to build interactive graphical user
    interfaces.
  • Specman Elite
  • Coupled with Seamless used to for verification of
    complex SOC designs
  • Enables test generation, checking, and coverage
    analysis to capture dependencies between hardware
    and software.

20
References
  • Seamless CVE Users and Reference Manual
  • /sw/mentor/cve_home/doc

21
  • Questions?
  • Thank You!
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