AIDA Front end electronics

1
AIDA Front end electronics

• Report July 2008
• Progress
• Virtex5 FPGA choice
• Milestones for prototype delivery

2
Progress

• Completed the FEE specification.
• Currently out for comments (1st July)
• Schematic capture started.
• FPGA part design.
• Processor peripheral component choices
• ML507 purchased and delivered
• Development kit with new FPGA.

3
Virtex5 FPGA choice

• Will Linux work and be useable in an FPGA without
  a processor ?
• Software development environment, Gbit rates,
  who else is doing it ?
• Can data channels share FPGA resources ?
• RAM and DSP blocks.

4
Experiences with ML507

• Xilinx development kit ML507 Virtex5-FXT70
  containing a PowerPC 440 with 256Mbyte RAM, Gbit
  ethernet and other peripherals
• DENX ELDK 4.1 Public domain Embedded Linux
  Development Kit gt cross compilers and tool
  kit for PPC 440
• Xilinx supply Linux kernel 2.6.25 with drivers
  for Virtex5 specific hardware (for example
  LLTemac - Gbit ethernet)
• Using the ELDK can configure and build the Linux
  kernel for the ML507 on a Linux workstation.
• Root file system via NFS on a standard server.
• This was working within a couple of days of
  receiving the ML507
• Clear advantage of using PPC processor and Linux

5
Experiences with ML507

• Testing network performance.
• Use standard test program from the MIDAS data
  acquisition suite which uses the data acquisition
  transfer library to send simulated data.
• Receiver is a Dell workstation running Linux with
  the MIDAS tape server receiver stage discarding
  received data. Block size 64 Kbytes.
• Data transfer rate 440 blocks/sec or
  28Mbyte/sec
• This took just as long as needed to compile the
  test program with the PC440 cross compiler.
• All MIDAS software etc will run within the PPC
  Linux processor

6
FPGA outline block diagram
7
FPGA resources

• Digital channel ( x 64 ) 4,217kbits
• Memory - 65kbits per channel
• Circulating buffer ( slow in fast out ) 1024x16
• Waveform store 3072x16
• Energy queue 10 x 36
• DSP - two
• MWD one for multiply and add
• Discriminator one for multiply and add
• Analog channels (one per ASIC) 65kbits
• Buffer memory 1024 x 16

8
FPGA choice

• Require
• Memory 4,282 kbits
• DSP 128
• SX95T
• Memory 8,576 kbits
• DSP 640
• No processor
• FX70T
• Memory 5,328 kbits
• DSP 128
• PowerPC 440 processor with large LINUX user
  community
• Both types are Virtex5 with the same pcb
  footprint. Further FPGAs with greater resources
  are planned.

9
Milestones for Prototype FEE delivery (Changes
included in blue)

• Complete Specification
• 1st July 2008 gt Achieved
• Complete Schematic and PCB layout
• 15th Sept 2008. gt Delayed
• Deliver 6 FEE cards ( 6 weeks )
• 27th Oct 2008 gt medium risk
• Complete Prototype VHDL
• 1st December 2008 gt Medium risk
• Commission FEE cards
• 1st February 2009 gt High risk

• Design ASIC Mezzanine
• 29th Sept 2008. gt Delayed
• Deliver 6 ASIC Mezzanines
• 17th Nov 2008 gt medium risk
• Assemble ASICs onto Mezzanines
• During Dec 2008 at Liverpool
• Complete Kapton board
• 1st February 2009 gt low risk