YODA Circuit Brainstorming

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YODA Circuit Brainstorming

• 10/22/04

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Opportunities in ULV design

• Circuit Yield-aware methodology to optimize the
  power, leakage, performance and variation of
  circuits under very low-voltage operation.
• Consider alternative logic style that may work
  better under ULV condition pass-transistor logic
  (non-regenerative)?
• Zero Vth logic operation (followed by shut-down
  in standby)
• Memory ULV SRAM standby / operation
• Optimization and error-tolerant design
• Other memory architectures?
• System
• Adaptive design tuning
• Asynchronous design (GALS)
• Error-tolerant schemes, such as redundancy
  techniques in FSM, etc

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Circuit Non-regenerative Logic Thrust

• Come up with a "logical effort"-like formulation
  for non-regenerative logic (pass-transistor and
  others)
• Derive simple analytical formulas for such logic
  for dynamic power, leakage, delay and their
  variations as a function of size, Vdd, Vth, temp,
  and process variations.
• Find the "canonical" gate for such logic
  (equivalent to inverter for static logic), and
  "canonical" closed-loop circuit (equivalent to
  ring-oscillator)
• Find a logic-to-circuit optimal mapping (CPL,
  DPL, PLA?)
• Find optimal values for Vdd, Vth, sizing similar
  to Dejan et al.'s work for static logic, compare
  optimal
• Compare regenerative with non-regenerative logic
  in terms of energy, delay, variations, etc,
  especially for very low Vdd.
• Optimal logic depth, activity factor, level of
  parallelism and/or pipelining, beyond Dejan's
  work, for both static and pass-xtor
• Look into advantages of the regularity of
  pass-xtor logic in terms of defect and
  fault-tolerance. Redundant rows with
  reconfiguration?
• Latch/flip-flop design for pass xtor logic
  (current sense?)
• Sinusoidal clock with skew-tolerant logic style?
• Optimal circuit design for above. Methodology?
• Later actual encoding/decoding algorithms
  implementation

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Circuit Zero Vth Thrust

• For static CMOS logic under ULV (250mV), what is
  the tradeoff in performance, active power and
  variation by reducing Vth?
• Should we achieve zero Vth by forward biasing
  (substrate leakage can be significant), or put
  the request on process?
• What is the Vth variation impact in such a
  scenario (zero Vth and low Vdd)?
• The above analysis on alternative logic
  (non-regenerative)?

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System Starting with Questions

• What are the operations required to accomplish
  sending and receiving data, the pruning of packet
  routing, encode/decode? This is related to what
  ppl in algorithm side's doing.
• What's the organization of the various components
  and sub-blocks (ie memory, function units, etc.)
  What memory bandwidth is required for the
  operations and how much storage space are needed
  (this is related to how many packets we need to
  buffer and how fast they are coming in)?
• How do we deal with run-time errors that happen
  in ULV circuit operation? How do we do the
  initial start-up tuning?
• What's the driving application for this type of
  network?? What mechanisms do we employ to get the
  sensor data out??

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System Some Thoughts on Steps We May Take

• Adaptive chip / block tuning
• What is the best method to test the performance
  of a functional block? Duplicate the longest
  path? Or design / synthesis a test vector set?
• How to design this adaptive testing interface
• What to be adaptively tuned? Clock period, Vth
  (body bias), Vdd, or any combination? Which one
  could be the most effective (least overhead in
  generating multiple level source)?
• GALS
• First to design a completion signal generation
  interface at the boundary of blocks.
• Next is the handshaking protocol between blocks
• What would be the best granularity in dividing
  our blocks in a chip (considering the overhead in
  adaptive tuning and asynchronous interface
• Error-tolerant design
• Due to reduced noise margin under ULV operation,
  the design needs to be robust when run-time
  errors occur.
• Examples of error-tolerant schemes that could be
  used redundancy in FSM, in registers (such as
  the razor FF approach), or computation function
  specific error correction algorithms.

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Questions to Our Network Team

• For Dragan et al. what are the likely functional
  elements (logic, arithmetic, finite-field,
  storage?)
• What are the operations required to accomplish
  sending and receiving data, the pruning of packet
  routing, encode/decode?