Lessons Learned from a Large Scale IEEE1588 Simulation

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Lessons Learned from a Large Scale IEEE1588
Simulation

• Georg Gaderer, Gerhard Siber, and Patrick
  Loschmidt

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Introduction

• Large scale Clock Synchronization
• Synchronize clocks remote over network
• Low bandwidth networks, with cascaded structure
  (e.g., PLC)
• Data collection without possibility to use
  transparent Clocks
• Quality Issues
• Synchronized clocks are a distributed control
  loop
• Power-up behavior
• Quality is lethal for the application (e.g.,
  accuracy of results in TM)

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Approach

• System Model
• General Means for Quality Monitoring
• Proposed Approach
• Applicability in Simulation of a real-live
  System

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Oscillator Model
Frequency f(t) as a function of time t
Environmental Term
Frequency Offset
Jitter Noise
Aging Factor
Phase Error
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Short-Term Noise

• Short term noise is typically normal-distributed,
  hence

25 MHz Oscillator,100ps/div, center 40 ns, 99k
Samples
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Quality of Clocks

• Problem Determine the local quality w/o
  reference clock
• Accuracy
• Precision
• ALLAN-deviation for phase-errors
• Time Interval error (TIE, MTIE)

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Possible Network Topologies

• Hierarchical network with Ethernet backbone
• Meshed Networks
• Line Topologies
• and heterogeneous structures

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Abstraction of Topology

• Large scale Networks
• Routed topology determined via spanning tree
• Hierarchical heterogenous networks
• IP-based backbone
• Power line-based Last Mile, maybe also
  cascaded on middle/low voltage
• Transparent Bridges not always possible

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ALLAN-Deviation in cascaded systems

• Accumulated phase-errors

. . .
Node p
Node q
. . .
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Simplifications

• Large number of samples N,
• Since the phase error is distributed around zero
• And taking Cauchy-Schwartz into account
• The ALLAN-deviation can be estimated as

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Upper and lower bounds (oscillator model)
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Simulator Details

• OmNet
• Simulator core
• C based
• Simple re-use of Open Source PTP stack
• Running as-is by replacement of System-calls
• Commercial stacks currently ported
• INET framework for IP-Backbone
• Graphical simulation setup of so-called modules
• NED Network description files
• Proper C model for existing HW-designs
• Visualization
• Built-in user interface for visualization
• Investigation of results
• Matlab

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Basic Simulation Model

• TODO

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Simulation Model

• Parameters from actual Node architectures
• High accurate, GPS-equipped grandmaster assumed
• IEEE1588 Access Points
• Chain of Boundary Clocks

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Simulation Results

• Power up behavior of nodes
• Raw (absolute) phase error
• Nodes behave (as one would expect) in a way that
  the last node has the least accuracy and needs
  the most time to synchronize

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Simulation Results

• Steady State
• Raw (absolute) phase error
• t ?200 sec after power up
• Quality of clocks is not determinable in this
  data-representation
• ALLAN-deviation

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Simulation Results
Samples taken in stable case
Samples taken during power-up
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Simulation Results
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Conclusion

• Quality Monitoring is vital for applications and
  use of synchronized clocks as a service for upper
  layers
• Cascaded structures lead to the problem that a
  node cannot determine its overall quality
• Proposed Solution
• ALLAN-Deviation
• Upper and lower border exist
• Quality can be observed in the stabilized and
  power-up case
• Short-term Measurements dynamic ALLAN deviation

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Why does it still work?! Power line Network

• Test setup

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Jitter in PLC Networks
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Implications

• Network Jitter is greater than the oscillator
  jitter
• Network several µs
• Oscillator several ns
• All, assuming reasonable (common) synchronization
  intervals (second-range)
• Nodes have are aware of clock adjustments
• E.g. speeding the clock up per 10 to adjust the
  actual value
• Synchronization messages have to consider the
  actual clock speed and approximate the error at
  the time sending

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Approximation approach

• Oscillator model
• Noise is not predictable
• Aging in the range of 0,1 Hz/s
• ? phase can be predicted by a linear
  approximation, if synchronization interval is gt
  1s