Chapter 7 Problems

1
Chapter 7 Problems
2

• Pins with the same name in the floorplan below
  are on the same net. Design a global route,
  equalizing channel utilization and wire lengths.

3

• For the floorplan and channel decomposition
  below
• Draw a channel graph.
• Give a feasible order for routing the channels.

4

• Which of the floorplans on the following page is
  a slicing structure? Explain.
• Can the floorplan below be routed with planar
  power and ground nets? If so, give a routing. If
  not, explain why

a) b)
5

• How much current can be supplied by a wide
  power line in a pad ring?
• How many output pads can be supported by a pad
  ring with a wide power line?
• A chip core is and
  requires 0.8 A. It needs 18
• signal input pad and 19 signal output pad
• How many are required
  assuming a 12 power
• ring?
• Will the total chip size be limited by the chip
  core or by the pad ring?
• Why doesn't an output pad require electrostatic
  discharge protection circuitry?
• A standard TTL load is 50 pF 
• If each stage of an output pad is 1.4 times
  larger than the previous stage, how large are the
  transistors in the pad's final stage such that
  the output pin's rise or fall time is no more
  than2 ns?
• How many stages are required to buffer a signal
  from a minimum-size inverter?

6

• Assume that a TTL-compatible output pad must
  produce 8 mA of current. 
• Counting only the output-stage current, how wide
  must the power lines be to support ten such
  output pads?
• What is a reasonable estimate of the total
  current required for each pad, including both
  intermediate drivers and the output stage? How
  much does this increase the required width of the
  power lines?