Template for MCMA Poster Slides

1
Single-Carrier Multiple-Antenna System
H.-M. Bluethgen2, D. Cabric1, K. Lu1, D.
Markovic1, S. M. Mishra2,A. S. Y. Poon1, C.
Shi1, H. Tang1, R. W. Brodersen1 1Berkeley
Wireless Research Center, UC Berkeley, 2Infineon
Technologies, Munich
2
Introduction

• Current research activities in MCMA group
  include
• Real-time emulation of a single-carrier
  multi-antenna system (SCMA) based on adaptive SVD
  algorithm
• Development of a parallel multi-antenna RF
  front-end
• Goals
• 1. Gain experience on
• System design including baseband and RF
  components
• Implementation of real-time radios
• 2. Develop a library of communication blocks
• Random number generators, channel, analog
  impairments,
• timing recovery, etc.
• 3. Get results using BEE as an emulation engine
• BER curves
• Influence of analog impairments

3
SCMA System Overview
Control
First Level of Hierarchy
SimulationControl
Second Level of Hierarchy
4x4-AntennaBaseband-EquivalentChannelModel
DataSource
DataSink
Analog Impairments
Analog Impairments
Phase/Timing Recovery
SVD
SVD
Transmitter
Channel
Receiver
Uplink
4
Specifications

• Data source 4 internal pseudo-random sequence
  generators
• Data rate 4 x 2 Mbps
• Bandwidth 1 MHz
• Modulation scheme QPSK
• Continuous transmission
• Control of channel coefficients, analog
  impairments parameters, SNR, start of
  transmission, freeze of simulation,etc.
• First implementation with wired uplink

5
Channel Emulation

• Use ray-tracing simulator BWRSim to determine
  impulse response between each antenna pair
• Extract a single tap for narrowband channel
• Repeat the procedure for each antenna location

• Channel coefficient matrix stored in block RAM
• Input parameter mobile speed
• 18 sec of data for 1 km/hr mobile speed fits on
  1 FPGA

6
Singular Value Decomposition (SVD) Based
Multiple-Antenna Processing

• LMS based blind tracking of SVD components U,?,V
  
• Key building blocks are based on vector
  additions and multiplications
• Investigate efficient implementation using
  time-multiplexing and interleaving
• Floating point to fixed point conversion to
  ensure minimal hardware cost
• Need to identify most efficient training
  strategy and optimal feedback rate
• Analyze performance in the presence of analog
  impairments

7
Analog Impairments
Transmitter impairments Pulse shaping filter
fixed point design D/A non-idealities Power
amplifier model RF filter model
Receiver impairments Frequency offset Phase
noise Low pass filtering Sampling phase jitter
Sampling phase offset I/Q imbalance amplitude
and phase
AWGN model using Cellular Automata Input Bits
precision Noise figure Periodicity gt
1010 Flat spectrum Seed initialized Low hardware
complexity lt1K slices
8
Parallel RF Front-End Overview
SCSI
Riser card
CLK
Scalable up to 16 antennas
Riser card
Control
SCSI
Riser card
9
Single Channel RF Front-End
Reference Design Specifications A/D and D/A
card 12 bits dual DAC _at_ 125Msps 12 bits dual
ADC _at_ 65Msps Clk signal from BEE BEE compatible
SCSI connection
RF front-end Carrier frequency of 2.4 GHz 20 MHz
channel bandwidth Linear PA with output power up
to 10 dBm AGC with gain 0 36 dB LNA gain
control Low phase noise SMA connectors for
antennas
Ref. Sig.
PLL Prog
Q In
I In
Q Out
Ant.
I Out
-5.2 V
GND
5.2 V
3.3 V
10
Future Work

• Complete first version of SCMA system
• Implement new angle-based multiple-antenna
  channel model
• Extend system to multiple carriers (OFDM)
• Design parallel front-end
• Establish wireless link using parallel front-end