Digital Sampling for Bird Radar

1
Digital Sampling for Bird Radar

• ECE 345
• Project Group 20
• Ryan Dawson
• Megan Yuill
• Cliff Kucharski

2
Introduction

• Prof. Larkin uses a mobile radar unit to track
  migrating birds, insects, etc.
• Radar emits 3 beam for 0.08 µs when a trigger
  pulse is issued
• A trigger pulse is received every 476 µs
• Current A/D Measurement Computing PCI-DAS4020/12
• --- 12 Bits
• --- 20 MHz maximum 1 kHz minimum
• Radar Resolution 7.5 m

3
Radar Operation
4
Current Set-up
5
Problems

• Currently the number of samples recorded by the
  DAQ
• computer cannot be chosen by the user
• Data approximately 2-3 km from the radar is too
  distorted for use due to the inverse square law
• --- Therefore, a signal twice as far from radar
  will be ¼ the intensity

6
Objectives

• Give the user the ability to choose the number of
  samples recorded after each trigger pulse
• Let the system operate with the A/D running
  continuously

7
Original Idea
8
New Problems

• Unable to access sampled data from Prof. Larkins
  A/D through the digital outputs
• Digital Samples only available on the PCI Bus
• Decided trying to access data on the PCI bus
  would be too invasive for Professor Larkins setup

9
New Solutions

• Decided to get a new A/D chip
• Specifications for new A/D
• -- minimum of 20 Msamples/s
• -- 12 bit data resolution
• -- TTL compatible

10
Updated Design
11
First A/D Choice

• Linear Systems LTC 1745
• 12-bit
• 25 MHz
• Better resolution than with Prof. Larkins A/D
• 6m versus 7.5m

12
LTC1745 Problems

• Too small for the machine shop to mount on a PCB
  board.
• Need 10 mils between pads
• 1 mil 0.0254 mm
• LTC1745 has 7.09 mils between pads

13
Texas Instruments ADS801

• 25 MHz sampling rate
• 5V typical supply voltage
• 6V maximum supply voltage
• 54 mA typical supply current
• 65 mA maximum supply current
• -40C to 85C specified temperature range

14
Input Circuit for ADS801

• For use with a single-ended input
• 0.25V to 4.25V rated
• 0.4V to 4.2V actual

15
Spartan XSA-100

• 8M x 16 SDRAM
• -- columns 512
• -- rows 4096
• -- banks 4
• 100 MHz programmable oscillator
• Parallel port
• 7-segment LED
• 84-pin prototyping interface
• 9V DC power jack
• 5V / 3.3V / 2.5V regulators
• Downloading cable

16
Safety Circuit
17
How does the logic work?

• FPGA logic is composed of the following elements
• one 12 bit shift register
• -- shifts in a 12 bit binary number
• two 12 bit comparators
• -- outputs logic1 when both 12 bit inputs are
  equal, logic0 otherwise
• two 12 bit counters, one 9 bit counters, one 2
  bit counter
• -- increments with positive-edge of a clock
  signal when enabled
• sdram controller
• control unit
• 2 clock dividers

18
VHDL
19
State Diagram
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PC Program

• PC pseudo-code.
• Main()
• initialize FPGA
• string date data or filename from user
• int sampleNum number of samples entered by
  user
• int endaddr (sampleNum128)1
• int cycleNum 0
• while(keyboard is not hit)
• // Set Register
• for(int i 12 i gt 0 i--)
• shift in next significant binary value from
  sampleNumber
• send StartSampling signal to FPGA

21
PC Side Program

• Microsoft Visual Studio C

22
Final Circuit
23
VHDL Development and Testing

• Used Xilinx Webpack 6.2
• -- VHDL design
• ModelSim
• -- Simulation/Troubleshooting
• GXS Tools
• -- Bring up on FPGA

24
VHDL Simulation Waveforms
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A/D Verification

• Externally clocked with a 3.3 Volt peak to peak,
  frequencies ranging from 1 kHz-20 MHz, square
  wave, DC offset of 1.6 V
• Input different waveforms
• -- AC signal needed DC offset
• Check voltage of input and output pins
• -- generally a logic high was around 2.25 V- 3V
• Used a set of 12 LEDs to see if certain digital
  outputs are not flashing

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Triangular Wave Data

• 2 Volts Peak to Peak
• 0.5 Hz

• 1000000000700070007000700070006E006E006E76
• 10001000006E006E00720072007200720072006268
• 1000200000200020002000200020002000200020D0
• 1000300000200020002000200020002000200020C0
• 1000400000200020002000200020002000200020B0
• 1000500000200020002000200020002000200020A0
• 1000600000310031003100360036003600360036EF
• 100070000033003300330033003300340034003FDA
• 1000800000FC00F600F200F200F200F200FA00F8C4
• 1000900000F800F800F800F800F500F500F501237D
• 1000A00001AE01AE01AE03FA03FA01AD01AD01AD3F
• 1000B00001AD01AD01AD01AD01AD01A501A501BFCE
• 1000C0000270027002760276027602760276027B77
• 1000D000027B027B027B027B02660266026602B63C
• 1000E0000360036003330333033303330333033306
• 1000F0000333033303330333033503350335036716
• 10010000042B042B042B042B042B042C042C06603E
• 100110000667042C04280428042804280428043929
• 1001200004F104F104F104F704F604F604F604F60D

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Square Wave Data

• 2 Volts peak to peak, 0.5 Hz

• 1000000006E706E706E706EA06EA06EA06EA06EA79
• 1000100006EC06EC06EC06EC06EC06E806E806EB59
• 1000200006FF06FF06FF06FF06FF06F606F606F6C3
• 1000300006F606F606E506E506E506E506E506E645
• 1000400006FD06FD06FD06FD06FB06FB06FB06FBA0
• 10005000042606E006ED06ED06ED06ED06F606EBD7
• 1000600006EC06EC06EC06FC06F406F406F406F4D0
• 1000700006F406E706E706E706E706E706F106F0F8
• 1000800006EA06EA06EA06F406F406F406F406F4BE
• 1000900006EF06EF06EF06EF06EF06E206E206EFD2
• 1000A00006F406F406F406F406F406F406F406F480
• 1000B00006F406EF06EF06EF06EF06EF06EF06E59D
• 1000C00021300570073006F306F306F306F306F059
• 1000D00006F006F006F006F006EF06EF06EF06EC77
• 1000E00006F706F506F506F506F506F506EB06EB4A
• 1000F00006EB06EB06EB06EF06EF06EF06EF06E96A
• 1001000006F606F306F306F306F306F306EE06EE2E
• 1001100006EE06EE06EE06FB06FB06FB06FB06F306
• 1001200006F606F606F606F606F606EF06EF06EF04

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Lab Testing
2 Volt Peak to Peak Square Wave, 0.5 Hz, 1.25 DC
offset Digital Representation of Input Voltage
(DataValue/4096)(Peak to Peak Voltage) (DC
offset 0.5(Peak to Peak Voltage))
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Obstacles

• Clocking difficulties
• Programmable I/O difficulties
• On A/D, certain digital output signals were
  unreliable
• _Inp() function call in windows XP
• FPGA unpredictable

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Conclusions

• More demanding engineering was required than
  originally anticipated
• OUR DESIGN WORKED !!
• However, certain components were too unreliable
  for use on a regular basis

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Cost
Part Cost Number Used Total Cost

XSA-100 250.00 1 250.00
ADS801 12.55 1 12.55
parallel cable 15.00 1 15.00
fuse 0.50 1 0.50
zener diode 0.50 1 0.50
0.1 uF Capacitor 0.10 1 0.10
22 pF Capacitor 0.10 1 0.10
50 ohm Resistor 0.10 1 0.10

Total Parts Cost Total Parts Cost 278.85
32
Recommendations/Improvements

• different FPGA
• professional manufacturing of Spartan II chip,
  SDRAM, and A/D on one board
• Remove extra circuitry for more efficient use

33
Acknowledgements

• We would like to thank the following
• ----- Professor Larkin ----- Greg
  Sorenson
• ----- Professors Carney and Swenson
• ----- Texas Instruments and Linear
  Systems for free samples
• ----- Jim Wehmer

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Questions ???????