Chapter 9 Memory Management

1
Chapter 9 Memory Management
2
Outline

• Background
• Logical versus Physical Address Space
• Swapping
• Contiguous Allocation
• Paging
• Segmentation
• Segmentation with Paging

3
9.1 Background
4
Background

• Program must be brought into memory and placed
  within a process for it to be executed.
• Input (job) queue collection of processes on
  the disk that are waiting to be brought into
  memory for execution.
• User programs go through several steps before
  being executed
• Figure 9.1 (Next slide)

5
Linking combine all the objectmodules of a
program into a binary program image
6
Steps for Loading a Process in Memory
System Library
static linking

• The linker combines object modules into a single
  executable binary file (load module)
• The loader places the load module in physical
  memory

System Library
dynamic linking
7
The Linking Function
Relocatable Object Modules
Load Module
8
Address Binding Mapping from one address space
to another

• Address representation
• Source program symbolic (such as count)
• After compiling re-locatable address
• 14 bytes from the beginning of this module
• After linkage editor or loader absolute address
• Physical memory address 74014

2000
0
int Igoto p1
p1
2250
250
Re-locatable Address
Symbolic Address
Absolute Address (Physical Memory)
9
Address Binding (Cont.)

• Address binding of instructions and data to
  physical memory addresses can happen at three
  different stages
• Compile time If memory location known a priori,
  absolute code can be generated
• Must recompile code if starting location changes
• MS-DOS .COM-format program
• Load time Must generate re-locatable code if
  memory location is not known at compile time
• Physical memory address is fixed during run time
• Must reload if starting location changes

10
Binding at Compile Time
Compile
Link
The CPU generates the absolute addresses
11
Binding at Compile Time (Cont.)
Load
12
Binding at Loader Time
Compile
Link
13
Binding at Loader Time (Cont.)
Load
The CPU generates the absolute addresses
14
Address Binding (Cont.)

• Execution time Binding delayed until run time
• The process can be moved during its execution
  from one memory segment to another
• The CPU generates the relative (virtual)
  addresses
• Need hardware support for address maps (e.g.,
  base and limit registers)
• Most general-purpose OS use this method
• Swapping, Paging, Segmentation

2000
15
Dynamic Relocation Using a Relocation Register
14000 to 14000MAX
Seen ByMemory Unit
Generated By CPU
0 to MAX
Binding at execution time (when reference is made)
Map LA to PA
16
Logical vs. Physical Address Space

• The concept of binding a logical address space to
  a physical address space is central to proper
  memory management
• Logical address generated by the CPU also
  referred to as virtual address
• Physical address address seen by the memory
  unit
• Logical and physical addresses are the same in
  compile-time and load-time address-binding
  schemes
• Logical and physical addresses differ in
  execution-time address-binding scheme

17
Memory-Management Unit (MMU)

• Hardware device that maps virtual to physical
  address.
• In MMU scheme, the value in the relocation
  register is added to every address generated by a
  user process (CPU) at the time it is sent to
  memory
• The user program deals with logical addresses it
  never sees the real physical addresses.

18
Dynamic Loading

• Routine is not loaded until it is called
• Better memory-space utilization
• Unused routine is never loaded.
• Useful when large amounts of code are needed to
  handle infrequently occurring cases
• Like error routines
• No special support from the operating system is
  required implemented through program design
• Responsibility of users to design dynamic-loading
  programs
• OS may help the programmer by providing library
  routines

19
Dynamic Linking

• The linking of some external modules is done
  after the creation of the load module (executable
  file)
• Windows external modules are .DLL files
• Unix external modules are .SO files (shared
  library)
• The load module contains references to external
  modules which are resolved either at
• Loading time (load-time dynamic linking)
• Run time when a call is made to a procedure
  defined in the external module (run-time dynamic
  linking)
• OS finds the external module and links it to the
  load module
• Check to see if the external module has been
  loaded into memory

20
Advantages of Dynamic Linking

• The external module is often a OS utility.
  Executable files can use another version of the
  external module without the need of being
  modified.
• Code sharing the same external module needs to
  be loaded in main memory only once. Each process
  is linked to the same external module.
• Saves memory and disk space
• Need OS to check if routine is in another
  processs memory address or that can allow
  multiple processes to access the same memory
  addresses
• OS is the only entity that can do so

21
Overlays

• Keep in memory only those instructions and data
  that are needed at any given time.
• Needed when process is larger than amount of
  memory allocated to it.
• Implemented by user, no special support needed
  from operating system, programming design of
  overlay structure is complex

22
Overlay (Cont.)
Pass 1 70K Pass 2
80K Sym. Table 20K Common Rou. 30K
Assembler
Total Memory Available 150K
23
9.2 Swapping
24
Swapping

• A process can be swapped temporarily out of
  memory to a backing store, and then brought back
  into memory for continued execution
• Round-robin swap out A, swap in B, and execute C
• Roll out, roll in swapping variant used for
  priority-based scheduling algorithms
• Lower-priority process is swapped out so
  higher-priority process can be loaded and
  executed
• Medium-term scheduler

25
Schematic View of Swapping
26
Swapping (Cont.)

• Backing store
• Fast disk large enough to accommodate copies of
  all memory images for all user
• Must provide direct access to these memory images
• The effect of address binding on swapping
• Binding at assembly or load time process cannot
  be moved to different locations
• Execution-time binding Its possible to swap a
  process into a different memory space

27
Swapping (Cont.)

• Situation Ready queue keeps all processes that
  are on the backing store or in memory and ready
  to runDispatcher checks if the scheduled process
  is in memory
• Context-switch time
• HD transfer rate 5 MB/Sec, avg. Latency 8
  millisecTransfer 1MB process to/from memory
  takes1MB/5MB per second 8 millisecond 208
  millisecondSwap in and out when context switch
  208 2
• Major part of swap time is transfer time
• Total transfer time is directly proportional to
  the amount of memory swapped
• Better to know exactly how many memory a process
  is using

28
Swapping (Cont.)

• Standard swapping is used in few systems
• Require too much swapping time and provide too
  little execution to be a reasonable memory
  management solution
• Modified versions of swapping are found on many
  systems, i.e., UNIX and Microsoft Windows.
• UNIX Start swapping if many processes were
  running and were using a threshold amount of
  memory
• I/O problem
• Latch job in memory while it is involved in I/O
• Do I/O only into OS buffers

29
9.3 Contiguous Memory Allocation
30
Memory Partition

• Main memory usually into two partitions
• Resident operating system, usually held in low
  memory with interrupt vector.
• User processes then held in high memory.

31
Memory Protection

• Protect user processes from each other, and from
  changing operating-system code and data
• Relocation-register scheme
• Hardware-support scheme
• Relocation register contains value of smallest
  physical address
• Limit register contains range of logical
  addresses each logical address must be less
  than the limit register.
• CPU dispatcher loads the relocation and limit
  registers with the correct values (stored in PCB)
  as part of the context switch

32
Hardware Support for Relocation and Limit
Registers
33
Memory Partition Allocation

• OS keeps a table about which parts of memory are
  available and which are occupied
• Hole block of available memory
• Holes of various size are scattered throughout
  memory
• When a process arrives, it is allocated memory
  from a hole large enough to accommodate it
• The hole is split into two parts (1) one for the
  arriving process, (2) one returned to the set of
  hole
• When a process terminates, its allocated memory
  is returned to the set of hole
• Maybe merged with adjacent holes

34
Memory Partition Allocation (Example)
OS
OS
OS
OS
process 5
process 5
process 5
process 8
process 2
process 2
OS
OS
OS
process 5
process 5
process 9
process 9
process 10
process 2
process 2
process 2
35
Dynamic Storage-Allocation Problem

• How to satisfy a request of size n from a list of
  free holes.
• First-fit Allocate the first hole that is big
  enough
• Best-fit Allocate the smallest hole that is big
  enough
• Must search entire list, unless ordered by size.
  Produces the smallest leftover hole.
• Worst-fit Allocate the largest hole
• Must also search entire list. Produces the
  largest leftover hole.
• First-fit and best-fit better than worst-fit in
  terms of speed and storage utilization
• May happen for memory and backing store

36
Example
37
Example (Cont.)
38
Fragmentation

• External fragmentation
• Total free memory space exists to satisfy a
  request, but it is not contiguous.
• Internal fragmentation
• Allocated memory may be slightly larger than
  requested memory. For example, consider a hole of
  18,464 bytes to allocate to a process with 18,462
  bytes
• This size difference is memory internal to a
  partition, but not being used.
• Also happen when physical memory is broken into
  fixed-sized blocks, and memory is allocated to
  processes in unit of block sizes
• Paging

39
Fragmentation (Cont.)

• Reduce external fragmentation by compaction
• Shuffle memory contents to place all free memory
  together in one large block
• Compaction is possible only if relocation is
  dynamic, and is done at execution time
• I/O problem
• Latch job in memory while it is involved in I/O
• Do I/O only into OS buffers

40
Internal Fragmentation
Its a overhead to maintain the information for a
hole of 2 bytes. OS allocate the all 18,464
bytes to next request Result in internal
fragmentation
41
Compaction (I)
42
Compaction (II)
43
Paging
44
Overview

• Paging permits the physical address space of a
  process to be noncontiguous
• Divide physical memory into fixed-sized blocks
  called frames
• Size is power of 2, between 512 bytes and 16MB
  bytes
• Divide logical memory into blocks of same size
  called pages
• Divide backing store into blocks of same size
• OS has to keep track of all free framesTo run a
  program of size n pages, need to find n free
  frames and load program from backing store

45
Overview (Cont.)

• OS must set up a page table to translate logical
  to physical addresses (address translation
  scheme)
• Each process has a page table
• A pointer to the page table is stored with the
  other registers in PCB
• CPU dispatcher loads the page table into the
  system-wide hardware page table (like PC and
  registers) as part of the context switch
• Paging suffers from internal fragmentation

46
Paging Example
47
Address Translation Scheme

• Address generated by CPU (logical address) is
  divided into
• Page number (p) used as an index into a page
  table which contains base address (or frame
  number) of each page in physical memory.
• Page offset (d) combined with base address to
  define the physical memory address that is sent
  to the memory unit.
• If the size of logical address space is 2m, and a
  page size is 2n

The page table has 2m-n entries
48
Another Paging Example
13
11 01
Physical space 25Logical space 24Page size
22PT Size 24/22 22Each PT entry needs 5-2
bits
2 4 1 9
9
010 01
49
Address Translation Hardware
If the size of physical space is 2l bytes, then
each entry of the PT has l-n bits
50
OS has to keep a free-frame list
51
Implementation of Page Table

• Page table is kept in main memory (kernel memory)
• Each process has a page table
• Page-table base register (PTBR) points to the
  page table
• Page-table length register (PTLR) indicates size
  of the page table (also for memory protection)
• Every data/instruction access requires two memory
  accesses
• One for the page table and one for the
  data/instruction
• Can be solved by the use of a special fast-lookup
  hardware cache called associative registers or
  translation look-aside buffers (TLBs)

52
Associative Register (Hardware)

• Associative registers parallel search
• Address translation (A, A)
• If A is in associative register, get frame
  out.
• Otherwise get frame from page table in memory

Typical of entries in a TLB 8 -- 2048
Page
Frame
TLB is the cache of page table
TLB has to be flushed when CS
53
Paging Hardware with TLB
54
Effective Access Time

• Associative Lookup ? time unit
• Assume memory cycle time is x time unit
• Hit ratio percentage of times that a page
  number is found in the associative registers
  ration related to number of associative
  registers.
• Hit ratio ?
• Effective Access Time (EAT)
• EAT (x ?) ? (2x ?)(1 ?)
• (2?) x ?

55
Effective Access Time (Cont.)

• Example 1
• Associate lookup 20
• Memory access 100
• Hit ratio 0.8
• EAT (100 20) 0.8 (200 20) 0.2 1.2
  100 20 140

• Example 2
• Associate lookup 20
• Memory access 100
• Hit ratio 0.98
• EAT (100 20) 0.98 (200 20) 0.02
  1.02 100 20 122

40 slow in memory access time
22 slow in memory access time
56
Memory Protection

• Memory protection implemented by associating
  protection bit with each frame
• read-only, read-write, execute-only
• Valid-invalid bit attached to each entry in the
  page table
• valid indicates that the associated page is in
  the process logical address space, and is thus a
  legal page.
• invalid indicates that the page is not in the
  process logical address space.

57
Memory Protection with Valid-Invalid bit

• A process with length 10,468
• 10468 12287 are also invalid
• PTLR

58
Page Table Structure

• Hierarchical Paging
• Hashed Page Tables
• Inverted Page Tables

59
Hierarchical Page Tables

• Break up the logical address space into multiple
  page tables.
• A simple technique is a two-level page table.

60
Two-Level Paging Example

• A logical address (on 32-bit machine with 4K page
  size) is divided into
• a page number consisting of 20 bits (32 - 12
  20)
• If each entry needs 4 bytes?220 4 bytes 4 MB
• a page offset consisting of 12 bits
• Since the page table is paged, the page number is
  further divided into
• a 10-bit page number.
• a 10-bit page offset.

• PT is also stored in memory
• Each frame can store 210 PT entries

61
Two-Level Paging Example (Cont.)

• Thus, a logical address is as followswhere p1
  is an index into the outer page table, and p2 is
  the displacement within the page of the outer
  page table.

62
Two-Level Page-Table Scheme
63
Address-Translation Scheme

• Address-translation scheme for a two-level 32-bit
  paging architecture

Memory Address A
A
64
Multilevel Paging and Performance

• A 64-bit logical address with 4K page size
• of PT entries 252 (64 -12 52)

65
Multilevel Paging and Performance

• Since each level is stored as a separate table in
  memory, covering a logical address to a physical
  one may take many memory accesses.
• Even though time needed for one effective memory
  access is increased, caching permits performance
  to remain reasonable.
• Cache hit rate of 98 percent yields (4-level PTs)
• effective access time 0.98 x 120 0.02 x 520
  128 nanoseconds.which is only a 28 percent
  slowdown in memory access time.

66
Hashed Page Tables

• Common in address spaces gt 32 bits
• The virtual page number is hashed into a page
  table. This page table contains a chain of
  elements hashing to the same location
• Virtual page numbers are compared in this chain
  searching for a match. If a match is found, the
  corresponding physical frame is extracted

67
Hashed Page Tables
68
Inverted Page Table

• One entry for each real page of memory.
• Entry consists of the virtual address of the page
  stored in that real memory location, with
  information about the process that owns that
  page.
• Decreases memory needed to store each page table,
  but increases time needed to search the table
  when a page reference occurs.
• Use hash table to limit the search to one or at
  most a few page-table entries.

69
Inverted Page Table Hardware
i1
i2
i3
Hash Table

• Hash table with ltpid, pgt as hash key

70
Inverted Page Table Example
Page 3
(P1)
Page 2
IPT
0
1
Page 1
2
6
0
3
Page 0
5
1
4
(P2)
2
2
5
0
3
6
7
71
Shared Pages

• Shared Code
• One copy of read-only (reentrant) code shared
  among processes (i.e., text editors, compilers,
  window systems).
• The reentrant nature of shared code should be
  enforced by OS (page protection)
• Shared code must appear in same location in the
  logical address space of all processes
• Inverted page tables have difficulties
  implementing shared pages
• Private code and data
• Each process keeps a separate copy of the code
  and data
• The pages for the private code and data can
  appear anywhere in the logical address space

72
Shared Pages Example
73
Segmentation
74
Segmentation

• Memory-management scheme that supports user view
  of memory.
• A program is a collection of segments. A segment
  is a logical unit such as
• main program,
• procedure,
• function,
• local variables, global variables,
• common block,
• stack,
• symbol table, arrays

75
Users View of A Program
76
Logical View of Segmentation
physical memory space
user space
1
2
3
4
77
Segmentation Architecture

• Logical address consists of a two tuple
• ltsegment-number, offsetgt
• Segment table
• base contains the starting physical address
  where the segments reside in memory
• limit specifies the length of the segment
• Segment-table base register (STBR) points to the
  segment tables location in memory
• Segment-table length register (STLR) indicates
  number of segments used by a program
• segment number s is legal if s lt STLR

78
Example of Segmentation
79
Segmentation Hardware
80
Segmentation Architecture (Cont.)

• Relocation
• Dynamic
• By segment table
• Sharing
• Shared segments
• Same segment number
• Since segments vary in length, memory allocation
  is a dynamic storage-allocation problem
• First fit/Best fit
• External Fragmentation

81
Segmentation Architecture (Cont.)

• Protection
• With each entry in segment table associate
• validation bit 0 ? illegal segment
• read/write/execute privileges
• Protection bits associated with segments code
  sharing occurs at segment level

82
Sharing of Segments
83
Segmentation with Paging MULTICS

• The MULTICS system solved problems of external
  fragmentation and lengthy search times by paging
  the segments.
• Solution differs from pure segmentation in that
  the segment-table entry contains not the base
  address of the segment, but rather the base
  address of a page table for this segment.

84
(No Transcript)
85
Segmentation with Paging Intel 386

• As shown in the following diagram, the Intel 386
  uses segmentation with paging for memory
  management with a two-level paging scheme.

• g select the segmentation (descriptor) table
• s index into the segmentation table
• p for protection

Selector
Segment Offset
13 1 2
s g p
Segment base
86
(No Transcript)
87
Comparing Memory-Management Strategies

• Hardware support
• Performance
• Fragmentation
• Relocation
• Swapping
• Sharing
• Protection