A Lowcomplexity RNS Multiplier

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A Low-complexity RNS Multiplier

• V. Paliouras, K. Karagianni, and T.Stouraitis
• Electrical and Computer Engineering Department
• University of Patras, Greece

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RNS Basics
Modulo mi operations
mod m1
mod m2
mod mM
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General RNS Architecture
mod m1
mod m2
Inverse Conversion
Forward Conversion
mod mM
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Modulo Multiplier Organization
A
B
Adder Array
Recursions of second stage
Adder Array
Adder Array
Adder Array
Final mapping
Conditional Addition
C
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Concept of the Proposed Approach
There exist couples/triples of input bits, such
that only one is asserted in a particular time,
for all possible inputs (residues).
The sum of such bits can be obtained by an OR
gate instead of an 1-bit HA/FA.
FA
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Formal Description of the Concept

• Let the input to a recursion be
• The bits form couples and triplets
  
• 
  such that

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An Optimization Procedure

• Objective to reduce the number of bits to be
  actually added in the ith column.

• Define, for each i, all
• Define, for each i, all
• From the several possible and find those
  that minimize
• denoted as and , for each of the
  columns.

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Adder Column Simplification in Proposed
Architecture
Bits the belong to couples and triplets of
and are processed by OR gates.
Conventional ith column
Proposed ith column
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A Modulo-5 Multiplier
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Area Complexity
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Area ? Time Savings Percentage