ECE 552 Image Toolbox Implementation

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ECE 552 Image Toolbox Implementation

• Team BLUE
• Dilip Patlolla
• Praneeth Parla
• Abhimanyu Sulakhe
• Prachya Mruetusatorn

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Overview

• Implement various Image Processing methods in
  FPGA hardware
• Application
• Simulate the techniques using MATLAB compiler on
  the image.

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Design Flow
System Requirements

Architectural Specifications
Behavioral Description
Structural Description
Pre Simulation
Synthesis
Libraries
Simulation
Placement and Routing
Physical Implementation
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Specifications

• Input Memory bank
• Logic Block
• Output Memory bank
• Clock divider
• Register

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Block Diagram
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Requirements

• VHDL Simulator
• C Compiler
• Virtex XUP Board
• IMParser.exe

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Enhancement Techniques

• Contrast Enhancement Method
• Smoothing of an Image.
• Brightness
• Darkness
• Intensity

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Contrast Enhancement Method

• An Image is taken and its contrast is
  increased or decreased as per the enhancement
  requirements of the Image.
• The required contrast enhancement is achieved
  applying the Histogram Stretching of the Image.

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Original Histogram
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After Contrast Enhancement
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(No Transcript)
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Smoothing

• A noisy Image is taken and the noise removal
  is done by applying a smoothing technique.
• The noise removal is achieved by using a mask
  which enables neighborhood pixel processing.

Original Image Smoothened
Image
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Brighten an Image
Brightened Image developed from original image by
increasing every pixel with a constant
Original Image
Brightened Image
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Original Image Histogram
Brightened Image Histogram
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Darken an Image
Darkened Image developed from original image by
decreasing every pixel with a constant
Original Image
Darkened Image
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Original Image Histogram
Darkened Image Histogram
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Threshold
Original Image High
Threshold
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TestBench and simulation
The testbench was developed using VHDL for full
coverage to test the logic_vhdl and ModelSim was
used for Simulation

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Threshold Incrementing
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Darkening an Image
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Flow Chart of Logic
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Block diagram using FPGA Adv
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RTL SChematic
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RTL SChematic
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Xilinx Layout
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Close in View of Layout
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Matlab/VHDL Brightness Results
original
Brightened
Differential Image
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Matab/VHDL Darkening results
Darkened Image developed from original image by
decreasing every pixel with a constant
Original Image Darkened Image
(vhdl) Differential image
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Matlab/VHDL Contrast Results
Original Image Contrasted
Image Differential image
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MATLAB/VHDL Threshold Results
Original Image High Threshold
VHDL MATLAB
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Smoothing an image
Original Image
VHDL Image
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Teamwork

• Dilip - Logic Function of intensity , contrast
  and smoothing(3x3 matrix)
• Abhimanyu- logic function of Darkness and
  Brightness
• Praneeth- Understanding ,verifying and writing
  testbenches for logic function, testing the
  bitfile on the board
• Prachya- Understanding ,verifying and writing
  testbenches for logic function , layout generation

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Implementation

• The main design has been implemented on
  VirtexIIPro FPGA
• ModelSim has been used to simulate and capture
  waveforms
• Implemented the design following the Design
  for Test strategies

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Problems faced

• The Imparser generated output pgm file is missing
  a parameter in its code.
• opening the image in wordpad and adding 255
  in the third line of the code of the image is
  doing the trick.Else its giving unknown decode
  error

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Time Division Statistics

• Understanding hw-2 10
• Writing Logic functions 15
• Bringing in 3x3 matrix 15
• Testbench and other stuff 5
• Bitfile Generation 30
• Time lost due to bugs 25

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Other images obtained during the project
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Thank you