ChihFan Liao and ShenIuan Liu

1
Design of Broadband CMOS Circuits for UWB and
High-Speed Wireline Receivers

• Chih-Fan Liao and Shen-Iuan Liu

Graduate Institute of Electronics
Engineering Department of Electrical
Engineering National Taiwan University
2
Outline

• Motivation
• A Broadband Noise-Canceling CMOS LNA for
  3.110.6-GHz UWB Receivers
• A 10-Gb/s CMOS AGC Amplifier with 35dB Dynamic
  Range for 10Gb Ethernet
• 40-Gb/s Transimpedance-AGC Amplifier and CDR
  Circuit for Broadband Data Receivers in 90nm CMOS
• A 40-Gb/s CMOS Serial-Link Receiver with Adaptive
  Equalization and CDR
• Conclusion

3
Motivation

• Broadband communication is an inevitable trend
• Wireless UWB, multi-standard, software-defined
  radio
• Wireline 10-/40-Gb/s optical and electrical
  systems
• CMOS is a good candidate for modern communication
  systems
• The intrinsic speed continues to improve
• The capability to integrate analog/RF with
  digital circuits

4
Conclusion

• The noise-canceling LNA and the proposed design
  approach are suitable for broadband wireless
  receivers such as UWB and multi-standard
  applications.
• A high-speed linear-in-dB VGA is proposed to
  facilitate the design of a 10-Gb/s CMOS AGC
  amplifier with wide DR.
• A 40-Gb/s transimpedance-AGC amplifier utilizes
  reversed triple-resonance networks and provides
  2kO gain and 520mVpp output swing.
• 40-Gb/s CDRs are realized in both half-rate and
  full-rate architectures
• A rotary-wave QVCO with direction-determined
  rotation is proposed in the half-rate CDR.
• The full-rate CDR is embedded in a serial-link
  receiver which performs data recovery with
  channel loss up to 10dB.