Logic Design Basic III

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Logic Design Basic III

• Instructor Koling Chang
• email kchang_at_cs.ucdavis.edu

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Outline

• Logic function simplification (cont.)
• Quine-McCluskey Method
• Generalized Gates
• Using Other Gates

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Quine-McCluskey Method

• Simplification involves two steps
• Obtain a simplified expression
• Essentially uses the following rule
• X Y X Y X
• This expression need not be minimal
• Next step eliminates any redundant terms
• Eliminate redundant terms from the simplified
  expression in the last step
• This step is needed even in the Karnaugh map
  method

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Quine-McCluskey Method (cont.)

• Steps to find prime implicants
• group minterms with same number of 1s.
• eliminate terms using the Simplification Law
• XYXY X
• between neighboring groups and generate new
  neighboring groups.
• repeat until this law can not be applied.

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Quine-McCluskey Method (cont.)

• Example
• f(a,b,c,e) S (0,1,2,5,6,7,8,9,10,14)
• Column I Column II Column III
• group 0 0 0000 0,1 000- 0,1,8,9 -00-
• group 1 1 0001 0,2 00-0 0,2,8,10 -0-0
• 2 0010 0,8 -000 0,8,1,9 -0-0 X
• 8 1000 1,5 0-01 0,8,2,10 -0-0 X
• group 2 5 0101 1,9 -001 2,6,10,14 --10
• 6 0110 2,6 0-10 2,10,6,14 --10 X
• 9 1001 2,10 -010
• 10 1010 8,9 100-
• group 3 7 0111 8,10 10-0
• 14 1110 5,7 01-1
• 6,7 011-
• 6,14 -110
• 10,14 1-10

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Quine-McCluskey Method (cont.)

• f acd abd abcbc bd cd
• Can you simplify this function using consensus
  theorem?
• XYYZXZ XYXZ
• b(ad)(ad)cbc badbc
• d(ab)(ab)cdc dabdc
• cbbdcd cbcd
• f abdbccd

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Quine-McCluskey Method (cont.)

• Prime Implicant Chart
• 0 1 2 5 6 7 8 9 10 14
• (0,1,8,9) bc X X X X
• (0,2,8,10) bd X X X X
• (2,6,10,14) cd X X X X
• (1,5) acd X X
• (5,7) abd X X
• (6,7) abc X X

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Generalized Gates

• Multiple input gates can be built using smaller
  gates
• Some gates like AND are easy to build
• Other gates like NAND are more involved

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Generalized Gates (cont.)

• Various ways to build higher-input gates
• Series
• Series-parallel
• Propagation delay depends on the implementation
• Series implementation
• 3-gate delay
• Series-parallel implementation
• 2-gate delay

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Multiple Outputs

• Two-output function
• A B C F1 F2
• 0 0 0 0 0
• 0 0 1 1 0
• 0 1 0 1 0
• 0 1 1 0 1
• 1 0 0 1 0
• 1 0 1 0 1
• 1 1 0 0 1
• 1 1 1 1 1

• F1 and F2 are familiar functions
• F1 Even-parity function
• F2 Majority function
• Another interpretation
• Full adder
• F1 Sum
• F2 Carry

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Implementation Using Other Gates

• Using NAND gates
• Get an equivalent expression
• A B C D A B C D
• Using de Morgans law
• A B C D A B . C D
• Can be generalized
• Majority function
• A B B C AC A B . BC . AC

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Implementation Using Other Gates (cont.)

• Majority function

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Implementation Using Other Gates (cont.)

• Bubble notation for even-parity function

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Implementation Using Other Gates (cont.)

• Using XOR gates
• More complicated
• A XOR B AB AB
• Even-parity example
• ABC ABC ABC ABC
• C(ABAB) C (AB AB)
• C(ABAB) C (ABAB)
• C(ABAB) C (ABAB)

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Proof of Last Two Lines

• (abab)
• (ab) (ab)
• (a b ) (ab)
• aa ab ba bb 0 ab ba 0
• ab ba

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Implementation Using Other Gates (cont.)

• Using XOR gates
• More complicated

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Proof of F2

• F2 BC AB AC
• BC AB(CC) AC(BB)
• BC ABC ABC ABC ABC
• BC A( BC BC)