HiDISC

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HiDISC Hierarchical Decoupled Instruction Set
Computer University of California, Irvine
HiDISC for DIS Applications
Compiler Driven Memory Hierarchy Management
while (not end of loop) y y (x h) send y
to SDQ

• A dedicated processor for each level of the
  memory hierarchy
• Explicit management of each level of the memory
  hierarchy using instructions generated by the
  compiler
• Hide memory latency by converting data access
  predictability to data access locality (Just in
  Time Fetch)
• Exploit instruction-level parallelism without
  extensive scheduling hardware
• Zero overhead prefetches for maximal computation
  throughput

Sequential Source
2-issue
Data Dependency Graph
Computation Processor Code
Computation Processor (CP)
Defining Load/Store Instructions
for (j 0 j lt i j) load (xj) load
(hi-j-1) GET_SCQ send (EOD token) send
address of yi to SAQ
Inner Loop Convolution
Registers
for (j 0 j lt i j) yiyi(xjhi-j-1)

Instruction Chasing for Backward Slice
3-issue
Access Processor (AP)
Access Stream
Computation Stream
L1 Cache
Access Processor Code
Cache Mgmt. Processor (CMP)
3-issue
for (j 0 j lt i j) prefetch
(xj) prefetch (hi-j-1 PUT_SCQ
Insert prefetch Instructions
Insert Communication Instructions
Access Code
Computation Code
Cache Management Code
HiDISC
Cache Management Code
HiDISC Stream Separator
Flexi-DISC System
Evaluating HiDISC

• Highly dynamic at execution time
• Dynamic reconfigurable central computational
  kernel (CK)
• Identical processing units for outer rings
  (LLCAR, MIR)

• Variety of target applications
• Highly efficient dynamic partitioning of the
  resources and their run-time allocation can be
  achieved

• DIS benchmarks perform extremely well- Enough
  floating-point operations to hide memory latency
• Good results for stressmarks (Pointer and
  Transitive Closure)- Not much in the AP depends
  on the results of CP

General-Purpose HiDISC